8-Bit Timer Block Diagram - Panasonic MN101L Series User Manual

8.1.2

8-bit Timer Block Diagram

8-bit Timer block diagram is shown in Figure:8.1.1
Timer 0, Timer 2 and Timer 4 are described "Timer n", Timer 1, Timer 3 and Timer 5 are described "Timer m".
HCLK
HCLK/4
HCLK/16
HCLK/64
M
HCLK/128
U
SYSCLK/2
X
SYSCLK/8
SCLK
TMmIO
TMmCK1-0 (TMmMD register)
TMmPSC1-0,TMmBAS (CKmMD register)
HCLK
HCLK/4
HCLK/16
HCLK/32 M
HCLK/64 U
SYSCLK/2 X
SYSCLK/4
SCLK
TMnIO
TMnCK1-0 (TMnMD register)
TMnPSC1-0,TMnBAS (CKnMD register)
matching detection
M
U
X
TMmCAS bit
(TMmMD register)
TMnOC register
matching
detection
TMnBC register
Overflow
Figure:8.1.1 Block Diagram of Timer n and Timer m
TMmOC register
TMmBC register
Timer m output
generation
Timer n output
generation
Chapter 8
8-bit Timer
TMmIO output
M
TMmIRQ interrupt
U
X
TMnIRQ interrupt
TMnIO output
Overview VIII - 3