Divwu 32-Bit / 16-Bit Division (Unsigned - Panasonic MN101L Series User Manual

2.4.4

DIVWU 32-bit / 16-bit division (unsigned)

DIVWU (MOV 0x04, (0x03F07))
{DW1, DW0} / A0
Operation
Divides the unsigned 32-bit value which is stored in the DW1 register (upper 16-bit) and DW0
register (lower 16-bit) by the unsigned 16-bit value of A0 register, and stores the quotient 16-
bit of the result in DW0 register and the remainder 16-bit of the result in DW1 register.
Bit Changes
If VF is "0"
VF: 0 (if the quotient is an unsigned
16-bit value)
NF: Set if the MSB of the quotient
is "1", otherwise set to "0".
CF: 0
ZF: Set if the MSB of the quotient is
"0", otherwise set to "0".
Execution of 32-bit / 16-bit division (unsigned)
1. Store the upper 16-bit of the dividend to DW1 register, the lower 16-bit of the dividend to DW0 register, and
the divisor to A0 register.
2. Execute MOV 0x04, (0x03F07) (Extended calculation macro instruction DIVWU).
3. The value of the unsigned 32-bit which is stored in the DW1 register (upper 16-bit) and DW0 register (lower
16-bit) is divided by the value of the unsigned 16-bit of A0 register. Then the quotient 16-bit of the result is
stored in DW0 register and the remainder 16-bit of the result is stored in DW1 register.
This extended calculation instruction is generated by the compiler for MN101L series by
appointing an option (-mmuldivw).
.. ..
When this extended calculation instruction is executed, the handy address (HA) is updated in
"0x03F07"
.. ..
→
DW0...DW1
If VF is "1"
VF: 1 (if the quotient is not an
unsigned 16-bit value)
NF: Undefined
CF: 0
ZF: Undefined
VF NF CF
0
Size, Cycles, Codes
6 nibbles
21 cycles
0000 0010 0111 0000 0100 0000
Extended Calculation Instruction
Chapter 2
CPU
ZF
II - 23