8-Bit Free-Running Timer; Operation - Panasonic MN101L Series User Manual

Chapter 10
General-Purpose Time Base/Free-Running Timer

10.3 8-bit Free-running Timer

10.3.1

Operation

8-bit Free-running Timer (Timer 6)
The generation cycle of the timer interrupt should be set in advance by selecting the clock source and setting the
compare register (TM6OC). When the binary counter (TM6BC) reaches the setting value of the compare register,
an interrupt request is generated at the next count clock and the binary counter is cleared to restart counting up
from 0x00.
Table:10.3.1 shows selectable clock sources.
Clock source
HCLK
SCLK
SYSCLK
HCLK/2
13
HCLK/2
SCLK/2
13
SCLK/2
f = 8 MHz, 4 MHz, 2 MHz
HCLK
f = 32.768 kHz
SCLK
f = f /2
SYSCLK HCLK
When SCLK is used as the clock source, the timer counts at "falling edge" of the count clock.
When other clock is used, it counts "rising edge" of the count clock.
.. ..
X - 8 8-bit Free-running Timer
Table:10.3.1 Clock Source at Timer Operation (Timer 6)
At f
HCLK
125 ns
250 ns
16 µs
7
1024 µs
7
One count time
= 8 MHz At f
HCLK
30.5 µs
2048 µs
3.9 ms
250 ms
= 4 MHz At f
250 ns
500 ns
32 µs
= 2 MHz
HCLK
500 ns
1000 ns
64 µs
4096 µs