Non-Maskable Interrupt (Nmi) Control Register - Panasonic MN101L Series User Manual

Chapter 3
Interrupts
3.2.1

Non-maskable Interrupt (NMI) Control Register

Non-maskable Interrupt (NMI) Control Register (NMICR: 0x03FE1)
When the undefined instruction is detected, IRQNPG is set to "1" and NMI occurs.
When the WDT overflows, IRQNWDG is set to "1" and NMI occurs.
bp
Bit name
At reset
Access
bp Bit name
7-3
2 IRQNPG
1 IRQNWDG
0 Reserved
IRQNPG is not cleared by hardware. Before RTI instruction is executed in the NMI interrupt
handler, they must be cleared.
.. ..
IRQNWDG is not cleared by hardware. Before RTI instruction is executed in the NMI inter-
rupt handler, they must be cleared.
..
..
III - 22 Control Registers
7 6
- -
0 0
R R
- Always read as "0".
Detection of Undefined instruction execution
0: Not detected
1: Detected
WDT overflow detection
0: Not detected
1: Detected
Must be set to "0".
5 4 3
- - -
0 0 0
R R R
Description
2 1
IRQNPG IRQNWDG
0 0
R/W R/W
0
Reserved
0
R/W