Timer Prescaler Selection Registers - Panasonic MN101L Series User Manual

8.2.1

Timer Prescaler Selection Registers

The timer prescaler selection registers select divided HCLK or SYSCLK as the count clock of 8-bit timer. In addi-
tion, these registers control the function of PWM output with additional pulses for Timer 0, 2 and 4.
Timer 0 Prescaler Selection Register (CK0MD: 0x03F76)
bp 7
Bit name -
At reset 0
Access R
bp Bit name
7 to 6 -
5 to 4 TM0ADD1-0
3 TM0ADDEN
TM0PSC1-0
2 to 0
TM0BAS
Timer 1 Prescaler Selection Register (CK1MD: 0x03F77)
bp 7
Bit name -
At reset 0
Access R
bp Bit name
7 to 3 -
TM1PSC1-0
2 to 0
TM1BAS
6 5
- TM0ADD1-0
0 0
R R/W R/W
Always read as 0.
Position of additional pulse (within 4 cycles of PWM basic waveform)
00: No pulse
01: At second cycle
10: At first and third cycle
11: At first, second and third cycle
PWM output with additional pulses control
0: Disabled (8-bit PWM output)
1: Enabled
Clock source select
000: HCLK/4
010: HCLK/16
100: HCLK/32
110: HCLK/64
X01: SYSCLK/2
X11: SYSCLK/4
6 5
- -
0 0
R R
Always read as 0.
Clock source select
000: HCLK/4
010: HCLK/16
100: HCLK/64
110: HCLK/128
X01: SYSCLK/2
X11: SYSCLK/8
4 3
TM0ADDEN
0 0
R/W R/W
Description
4 3
- -
0 0
R R R/W
Description
2 1
TM0PSC1-0 TM0BAS
0 0
R/W R/W
2 1
TM1PSC1-0 TM1BAS
0 0
R/W R/W
8-bit Timer Control Registers
Chapter 8
8-bit Timer
0
0
0
0
VIII - 5