8-Bit Timer; Operation - Panasonic MN101L Series User Manual

8.3 8-bit Timer

8.3.1

Operation

In the 8-bit timer operation, the timer can generate interrupts periodically.
8-bit Timer Operation (Timer 0 to Timer 5)
The interrupt generation cycle of the timer is determined by selecting the clock source and setting the value of
TMnOC, in advance. When the value of TMnBC matches the setting value of timer n compare register, an inter-
rupt request is generated at the next count clock. Then, the timer n binary counter is cleared and restarts counting
up from "0x00".
The clock source can be selected depending on timers as shown in the table below.
Clock source
HCLK
HCLK/4
HCLK/16
HCLK/32
HCLK/64
HCLK/128
SYSCLK/2
SYSCLK/4
SYSCLK/8
SCLK
f =10 MHz, f
HCLK SCLK
f = HCLK/2 = 5 MHz
SYSCLK
When using SCLK as a clock source, the timer counts at the falling edge of the count clock.
When using other clocks, the timer counts at the rising edge of the count clock.
.. ..
Time per Count Timer 0
√
100 ns
√
400 ns
√
1.6 µs
3.2 µs √
6.4 µs √
12.8 µs
-
√
400 ns
√
800 ns
1600 ns -
√
30.5 µs
=32.768 kHz
Timer 1 Timer 2 Timer 3
√ √ √
√ √ √
√ √ √
√
-
√ √ √
√ √
-
√ √ √
√
-
√ √
-
√ √ √
Timer 4 Timer 5
√ √
√ √
√ √
√
- -
√ √
√
-
√ √
√
- -
√
-
√ √
8-bit Timer
Chapter 8
8-bit Timer
VIII - 15