Group Interrupt Control Register Setup - Panasonic MN101L Series User Manual

3.1.4

Group Interrupt Control Register Setup

Setup PERInDT (n = 0, 1) by Software
The each bit of the PERInDT is set to "1" by the hardware and software, and cleared to "0" only by software.
When the interrupt occurs, the corresponding bits is set to "1", and the maskable interrupt occurs depending on the
setting of the each bit of PERInEN.
Above bits can be set to "1" by software, and it generates the maskable interrupt.
Unlike xICR.IR, each bit of PERInDT is not cleared by hardware, and needs to be cleared by software.
The each bit of PERInDT is changed as the following table.
Value before write
0
0
1
1
When clearing all bits of the PERInDT, read the value of PERInDT first, and then write the
same value to PERInDT.
.. ..
Each bit of PERInDT is not cleared by hardware, and needs to be cleared by software.
.. ..
Don't change the bit of PERInICR, while the corresponding bit of the PERInEN and the PER-
InDT is "1". When changing PERInICR, the interrupt may be accepted unintentionally.
.. ..
When the two events, one is that an interrupt trigger causes PERInDT.DTm to be set to "1"
and the other is that PERInDT.DTm is set or cleared by software, occur at the same time, the
value of software is set in PERInDT.Dm.
..
..
Write data Value after write
0
1
0
1
Value change
0 Not changed
1 Bit is set
1 Not changed
0 Bit is cleared
Chapter 3
Interrupts
Overview III - 17