Overview - Panasonic MN101L Series User Manual

Chapter 17
LCD

17.1 Overview

This LSI has an LCD driver circuit (LCDDRV) which is composed of 43 segment output pins and 4 common out-
put pins (39 segment output pins and 8 common output pins). The LCDDRV has an LCD reference voltage circuit
(REFVOL) and a voltage booster circuit (BSTVOL).
Table:17.1.1 shows the functions of LCDDRV.
Duty
LCD Power Supply
LCD Reference Voltage Circuit (REFVOL)
LCD Voltage Booster Circuit (BSTVOL)
Clock Source for LCD Display (LCDCLKS)
LCD Display Clock (LCDCLK)
Clock Source for BSTVOL (LCUPCKS)
Boost Clock for BSTVOL (LCUPCK)
LCDCLKS : Selected clock with LCDMD3.LCCKS2-0
LCDCLK : Selected clock with LCDMD3.LCCK3-0
LCUPCKS : Selected clock with LCDMD0.LCUPCKS2-0
LCUPCK : Selected clock with LCDMD0.LCUPCKDIV2-0
LCD operations are restricted depending on the CPU mode which is shown in Table:17.1.2.
√: LCD operation is enabled ∆: Displaying data can be maintained. −: LCD operation is disabled.
The supply voltage to VLC1 (V
(V
DD30
When LCDDRV is not used, Supply V
..
are used as general-purpose ports.
..
XVII - 2 Overview
Table:17.1.1 LCD Functions
Function
Table:17.1.2 LCD Function Restrictions in Each CPU Mode
CPU Mode
Operation Mode
Standby Mode
HALT2/HALT3
STOP0/STOP1
≤ V ≤ 3.6 V).
LC1
Static
1/2 to 1/8 duty
V ,V , V
LC1 LC2 LC3
0.05 V increments within a range of 0.9 V to 1.8 V
Boosts reference voltage input by 2, 3 times.
4 5
SCLK, HCLK/2 , HCLK/2 , HCLK/2
3 4
LCDCLKS/2 , LCDCLKS/2 , LCDCLKS/2
8 9
CLKS/2 , LCDCLKS/2 , LCDCLKS/2
4 5
SCLK, HCLK/2 , HCLK/2 , HCLK/2
LCUPCKS × 1/8, LCUPCKS × 1/16, LCUPCKS × 1/32,
LCUPCKS × 1/64, LCUPCKS × 1/128
Clock Source for LCDCLKS
Clock Source for LCUPCKS
HCLK-based
NORMAL
SLOW
HALT0
HALT1
) must be kept between V
LC1
to VLC1 pin. At this time, VLC2/VLC3/C1/C2 pins
DD30
Details
6 7 8
, HCLK/2 , HCLK/2
5 6
, LCDCLKS/2 , LCDCLKS/2
10 11
, LCDCLKS/2 , LCDCLKS/2
6 7 8
, HCLK/2 , HCLK/2
SCLK-based
√ √
√
-
∆ ∆
∆
-
∆
-
- -
and 3.6 V.
DD30
7
, LCD-
12