Gem1 Ethernet; Ethernet Phy (Three Resets) - Xilinx VCK190 Series User Manual

A PS Gigabit Ethernet MAC (GEM) implements a 10/100/1000 Mb/s Ethernet interface (see the
figure in PMC MIO[49] and LPD_MIO[12:25]: GEM1
DP83867IRPAP U198 Ethernet RGMII PHY before being routed to a vertical dual-stacked RJ45
Ethernet connector J307 (upper receptacle). The RGMII Ethernet PHY is boot strapped to PHY
address (0x01) and Auto Negotiation is set to Enable.
PMC MIO[49] and LPD_MIO[12:25]: GEM1 Ethernet
[Figure 3, callout 17]
A PS Gigabit Ethernet MAC (GEM) implements a 10/100/1000 Mb/s Ethernet interface (see the
following figure), which connects to TI DP83867IRPAP U134 Ethernet RGMII PHY before being
routed to a vertical dual-stacked RJ45 Ethernet connector J307 (lower receptacle). The RGMII
Ethernet PHY is boot strapped to PHY address (0x02) and Auto Negotiation is set to Enable.
The following figure shows the dual Ethernet topology.
XCVC1902
ACAP

Ethernet PHY (Three Resets)

[Figure 3, callout 35]
Each DP83867ISRGZ PHY (GEM0 U198, GEM1 U134) is reset by its GEMx_RESET_B generated
by dedicated pushbutton switches and PMC_MIO signals as shown in the following figure. The
POR_B signal generated by the TPS389001DSER U10 POR device (activated by pushbutton
SW2) is wired in parallel to each Ethernet PHY reset circuit.
UG1366 (v1.0) January 7, 2021
VCK190 Board User Guide
Figure 16: Dual RGMII Ethernet
GEM0 U198
RGMII
DP83867IR
10/100/1000
MDIO
PHY
GEM1 U134
RGMII
DP83867IR
10/100/1000
MDIO
PHY
Chapter 3: Board Component Descriptions
Ethernet), which connects to TI
MII
25 MHz
Crystal
MII
25 MHz
Crystal
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J307
Upper
RJ45
J307
Lower
RJ45
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