Audio Serial Data Format; Iis-Bus Format; Msb (Left) Justified - Samsung S5PC110 Manual

S5PC110_UM 2 IIS MULTI AUDIO INTERFACE

2.5 AUDIO SERIAL DATA FORMAT

2.5.1 IIS-BUS FORMAT

The IIS bus has four lines including serial data input I2SSDI, serial data output I2SSDO, left/right channel select
clock I2SLRCLK, and serial bit clock I2SSCLK; master generates I2SLRCLK and I2SSCLK.
Serial data is transmitted in 2's complement with the MSB first with a fixed position, whereas the position of the
LSB depends on the word length. The transmitter sends the MSB of the next word at one clock period after the
I2SLRCLK is changed. Serial data sent by the transmitter can be synchronized either with the trailing or with the
leading edge of the clock signal.
The LR channel select line indicates the direction of left or right channel being transmitted. I2SLRCLK may be
changed either on a trailing or leading edge of the serial clock, but it does not need to be symmetrical. In the
slave, this signal is latched on the leading edge of the clock signal. The I2SLRCLK line changes one clock period
before the MSB is transmitted. This allows the slave transmitter to derive synchronous timing of the serial data
that will be set up for transmission. Furthermore, it enables the receiver to store the previous word and clear the
input for the next word.

2.5.2 MSB (LEFT) JUSTIFIED

MSB-Justified (Left-Justified) format is similar to IIS bus format, except that in MSB-justified format, the transmitter
always sends the MSB of the next word at the same time whenever the I2SLRCLK is changed.
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