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6.8.1.3
Ethernet Ports
The integrated I/O port supports two Ethernet ports and uses the twisted-
pair (10baseT) connection. The Ethernet port can sustain reception of
back-to-back packets at full line speed with a 9.6 µs IPG (interpacket gap),
or to transmit such back-to-back packets, due to its on-chip dual 256-byte
FIFOs.
6.8.1.4
Optional NVRAM Daughter Card
NVRAM is a memory module (DJ-ML300-BA) used on the PCI local bus,
which provides for the retention of data in the event of system failure. The
caching software can use the NVRAM module to enhance the performance
of applications in synchronous disk I/O. The integrated I/O port NVRAM
daughter card has a capacity of 4 Mbytes.
6.8.2 Integrated I/O Section Transactions
The HPC gate array communicates over the internal hose (hose 0) inter-
face using four types of transactions:
6.8.2.1
DMA Transactions
All PCI DMA transactions access the HPC as a PCI target. PCI memory
transactions are forwarded to the Up Hose if they access one of the address
ranges specified by a set of DMA window registers. If required, the PCI
DMA address is translated to a system memory address through a scat-
ter/gather address map. The HPC can generate DMA read and masked/
unmasked write transactions to the Up Hose. The HPC generates an in-
terlocked read transaction to the Up Hose in response to a PCI DMA read
with PCI lock asserted.
DMA write transactions are received from the PCI bus in a store and for-
ward manner. The HPC generates masked octaword or hexword writes, or
unmasked double hexword writes to the HDR gate array. Each HPC con-
tains two PCI DMA write buffers allowing one transaction's write data to
be transferred over the Up Hose while another PCI DMA command is be-
ing received from the PCI bus. All DMA read transactions are the size of
the system memory block, which is 64 bytes. DMA read commands sent to
the HDR are tagged with an HPC ID code. Read return data received over
the Down Hose bus is identified by its tag and buffered by the appropriate
HPC. Each HPC contains one 64-byte read return buffer. The buffer is
filled from the Down Hose until a cut-through threshold is reached, at
which point the HPC begins transferring data on the PCI. The PCI trans-
fer proceeds in parallel with the remainder of the hose transfer.
• DMA
• Mailbox
• CSR
• Interrupt
I/O Port 6-83
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