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Table 7-55 ICCMSR Register Bit Definitions (Continued)
Name
Bit(s)
<1:0>
ARB_CTL<1:0>
Type
Function
R/W, 0
ARB_CTL
00 (Cont)
Function
If the I/O port does not issue a
back-to-back request to the same
memory bank, that is, at least one
potential request cycle to that
memory bank occurs, then the
next request to that memory bank
by the I/O port can be initiated
through TLSB_REQ8_HIGH.
Thus, if the I/O port requests
back-to-back transactions to the
same bank, it will arbitrate the
second transaction at TLSB_
REQ8_LOW. At all other times it
will arbitrate at TLSB_REQ8_
HIGH. This guarantees that the
I/O port wins its arbitration al-
most 100% of the time. It also
guarantees that the I/O port can-
not lock out a memory bank.
NOTE: If the I/O port loses at
TLSB_REQ8_LOW, it switches to
TLSB_REQ8_HIGH on the next
cycle. Write Unlocks always use
TLSB_REQ8_HIGH, regardless of
the previous arbitration request cy-
cle.
This mode guarantees minimum
latency to I/O devices located on
remote nodes such as the XMI or
Futurebus+.
This is the normal default mode.
System Registers 7-115
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