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Table 7-4 TLBER Register Bit Definitions (Continued)
Name
Bit(s)
<16>
UDE
<15:11>
RSVD
<10>
ATDE
<9>
REQDE
<8>
FNAE
<7>
MMRE
7-10 System Registers
Type
Function
W1C, 0
Uncorrectable Data Error. Set when
<UECC> is set in any TLESRn register. This is
a hard error that asserts TLSB_DATA_ ERROR.
CPU: Set when <UECC> is set in any TLESRn
register.
I/O: Posts an IPL 17 error interrupt if inter-
rupts are enabled.
R, 0
Reserved. Read as zeros.
W1C, 0
Address Transmitter During Error. A status
bit set when FNAE, NAE, APE, or ATCE errors
are detected if node was the transmitter of the
command, address, and bank number during the
address bus sequence.
Memory: Not implemented.
I/O: <ATDE> is set also on BAE error.
W1C, 0
Request Deassertion Error. Set when a re-
quest signal is not deasserted by a node that has
won address bus arbitration. This is a system
fatal error that asserts TLSB_FAULT.
Memory: Not implemented.
W1C, 0
Fatal No Acknowledge Error. Set when a
commander fails to receive a TLSB_CMD_ACK
response for a memory access command. This is
a system fatal error that asserts TLSB_FAULT.
Memory: Not implemented.
W1C, 0
Memory Mapping Register Error. Set when
a commander node detects an error translating a
physical address to a bank number. An improp-
erly initialized TLMMRn register will normally
be the cause. This bit will be set when no bank
number is found. This is a commander specific
error and handling of the error is node specific.
If the address is issued on the bus, the command
must be no-op.
Memory: Not implemented.
I/O: Does not issue address on the bus and
posts IPL 17 interrupt if interrupts are enabled.
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