Table of Contents
Advertisement
Table 7-28 TLEPMERR Register Bit Definitions (Continued)
Name
Bit(s)
<2>
D2MCPE
<1>
A2MAPE1
<0>
A2MAPE0
Type
Function
W1C, 0
DIGA to MMG CSR Parity Error. Set when the
MMG detects a parity error on the DIGA to DIGA CSR
bus. This error can occur when a CSR in the MMG is
being written or read. This error can be detected on
either CSR data or CSR command/address informa-
tion, but only when MMG's DCSR valid bit is asserted,
or during a DIGA0 to MMG data movement. This error
indicates that CSR data has been corrupted. This is a
hard error and causes a machine check.
W1C, 0
ADG to MMG Address Parity Error #1. Set when
the MMG detects a parity error on the ADG to
MMG/CPU1 address bus. This error can only occur
when ADG is driving the CPU1 CMD<3:0> wires and
the MMG ADDR<17:0>. This error causes the CPU
module to assert a machine check interrupt to
DECchip 21164 (both). In general, however, the CPU1
detects this error on chip as well. This error renders
CPU1 incapable of servicing the system command that
generated the error. This in turn could result in a
TLSB DTO error and cause the assertion of
TLSB_FAULT. This is a system fatal error.
W1C, 0
ADG to MMG Address Parity Error #0. Set when
the MMG detects a parity error on the ADG to
MMG/CPU0 address bus. This error can only occur
when ADG is driving the CPU0 CMD<3:0> wires and
the MMG ADDR<17:0>. This error causes the CPU
module to assert a machine check interrupt to
DECchip 21164 (both). In general, however, the CPU0
detects this error on chip as well. This error renders
CPU0 incapable of servicing the system command that
generated the error. This in turn could result in a
TLSB DTO error and cause assertion of
TLSB_FAULT. This is a system fatal error.
System Registers 7-61
Advertisement
Table of Contents
