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mation between the TLSB and I/O adapter modules by transmitting and
receiving packets across the hose(s). Mailbox, I/O window, device inter-
rupt, DMA read/IREAD, and NVRAM write transactions (see following
subsections) consist of packet pairs: a command packet and a status re-
turn packet.
Some transactions occur local to the I/O port and do not involve hose pack-
ets. These transactions include CSR reads/writes and error interrupts. All
I/O port CSRs are accessible from the TLSB through the CSR read and
CSR write commands. Error interrupts are generated to the CPU(s) if an
error is detected internal to the I/O port. As a result, the interrupt trans-
action is generated and ended entirely within the I/O port. No Interrupt
packet is received on the Up Hose, and no INTR/IDENT status return
packet is sent back on the Down Hose.
Table 6-1 summarizes the various transaction types supported by the I/O
port and indicates the hose packets required to implement each transac-
tion.
The I/O port can pipeline up to two DMA transactions at a time. This al-
lows the I/O port to achieve a throughput of 500 Mbytes/sec of raw data.
The CSR data size on the TLSB is a hexword (256 bits). Valid bits on the
second data cycle of CSR writes define which longword(s) of the hexword
are valid.
6-4 I/O Port
• The mailbox transaction consists of a Mailbox Command packet and a
Mailbox Status Return packet.
• Window read transactions are made up of window read command pack-
ets followed by window read data return packets.
• Window write transactions are made up of window write command
packets followed by window write status return packets.
• Device interrupt transactions consist of an INTR/IDENT command
packet followed by an INTR/IDENT status return packet.
• The DMA read/IREAD transactions are made up of a DMA
read/IREAD request packet followed by a DMA read data return
packet.
• DMA write/Wmask transactions are "disconnected" (that is, write-and-
run) and therefore have no return status packet.
• An extended NVRAM write transaction consists of a Memory Channel
write packet followed by a window write status return packet.
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