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Table 7-55 ICCMSR Register Bit Definitions (Continued)
Name
Bit(s)
<3:2>
SUP_CTL<1:0>
<1:0>
ARB_CTL<1:0>
7-114 System Registers
Type
Function
R/W, 0
SUP_CTL
11
Arbitration Control. This field can be pro-
R/W, 0
grammed to select the manner in which the I/O
port installed in node 8 arbitrates for the TLSB.
This field has no effect on an I/O port in any
other slot.
NOTE: Potential_REQ_CYCLE = IDLE_CYCLE
or ARB_CYCLE+1 and not ARB_SUPRESS and
not RCV_REQ8_HIGH.
ARB_CTL
00
Function
Suppress after 2 transactions. If
the I/O port detects 2 outstanding
transactions pending on the
TLSB, it asserts TLSB_ARB_
SUP during the command/ ad-
dress cycle of the second transac-
tion for one cycle, then deasserts
it for one cycle. It repeats this
two-cycle sequence until arbitra-
tion can be permitted again, that
is, when fewer than 2 outstand-
ing transactions are pending.
Function
Minimum latency mode (default).
When the I/O port wins the bus ar-
bitration and accesses a particular
memory bank, its next request to
that same memory bank will arbi-
trate on TLSB_REQ8_LOW if it is
a back-to-back request. A back-to-
back request is when the I/O port
arbitrates for the same bank on
the first allowable cycle after that
bank's TLSB_BANK_AVL line is
asserted.
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