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Table 7-43 MCR Register Bit Definitions (Continued)
Name
Bit(s)
<5:4>
DTR
<3:2>
STRN
<1>
RSVD
<0>
DTYP
1 Value loaded into register at system initialization/reset through manufacturing installed jumpers on the module.
7-92 System Registers
Type
Function
R/W, 0
DRAM Timing Rate. This field is used to mod-
ify the DRAM timing and refresh rate. At reset,
DRAM timing defaults to supporting a 10 ns bus
cycle time, while the refresh rate defaults to sup-
porting a 30 ns bus. <DTR> is normally written
by console through a TLSB broadcast write com-
mand. This ensures that all memories will re-
main syncronized as to when they refresh the
DRAMs. The <DTR> field should not be changed
from the value set by console when other bits in
this field are modified.
DTR
00 (Def)
01
10
11
1
R, X
Strings Installed. This field supplies informa-
tion about the number of strings installed on a
module.
STRN
00
01
10
11
R0
Reserved. Read as zero.
1
R, X
DRAM Type. This field supplies information
about what size DRAM technology is being used;
this together with the number of strings in-
stalled determines module capacity.
DTYP
0
1
Bus Speed
Refresh Counter
Range
Value
10.0 - 11.2
1360
Reserved
None
12.5 - 13.7
1088
13.8 - 15.0
1008
Strings
1
2
4
8
DRAM Type
4 Mbit
16 Mbit
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