DEC AlphaServer 8200 Technical Manual page 381

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Self-Test Error in MDI0 bit, 7-96
Self-Test Error in MDI1 bit, 7-96
Self-Test Error in MDI2 bit, 7-96
Self-Test Error in MDI3 bit, 7-96
Self-Test Error register, 7-95
Self-Test error reporting, 4-18
Self-Test Failing Address Range bits, 7-93
Self-Test Fail A bit, 7-16
Self-Test Fail B bit, 7-16
Self-test modes, memory, 4-17
Self-test operation, memory, 4-18
Self-Test Passed bit, 7-83
Self-Test Pattern Select bit, 7-107
Self-test performance, 4-19
Self-test times, 4-19
Self-test, memory, 4-16
SEND_DATA timeout errors, 2-40, 6-73
SEQE, 7-8
Sequence Error bit, 7-8
Sequence numbers, 2-20
Sequence number errors, 2-20
Serial Clock bit, 7-86, 7-141
Serial EEPROM Control/Data register, 7-86
Serial ROM Clock bit, 7-84
Serial ROM port, 3-5
Servicing interrupts, 8-5
Set Voltage Down bit, 7-62
Set Voltage Up bit, 7-62
Shared bit, 7-91
SHRD, 7-91
Single Bank bit, 7-21
Single-bit ECC errors, 2-40, 6-72
Software, 1-6
Software Revision field, 7-5
Soft TLSB errors recovered by hardware, I/O
port, 6-66
Source Address bits, 7-75
Sparse address mapping, 6-37
Sparse address space, 6-19
Sparse address space reads, 6-15
Sparse address space writes, 6-17
Sparse address space write data, 6-18
Sparse address write length, 6-20
Sparse space reads and writes, 3-12
Sparse window read command packet, 6-45,
6-46
Sparse window read data, 6-16
Sparse window read data return packet, 6-61,
6-62
Sparse window write command packet, 6-46,
6-47
Sparse window write command packet
description, 6-48
SRC_ADR<38:9>, 7-75
SROM_CLK, 7-84
STAIR, 7-93
STAIR register, 7-93
STATUS, 7-34
STDERA, 7-104
STDERB, 7-104
STDERC, 7-104
STDERD, 7-104
STDERE, 7-105
STDERX register, 7-103
STER register, 7-95
STE0, 7-96
STE1, 7-96
STE2, 7-96
STE3, 7-96
STF_A, 7-16
STF_B, 7-16
STP, 7-83
Strings Installed bits, 7-92
STRN, 7-92
Suppress Control bits, 7-113
SUP_CTL<1:0>, 7-113
SWREV, 7-5
Syndrome 0 bits, 7-28
Syndrome 1 bits, 7-28
SYND0, 7-28
SYND1, 7-28
SYSDERR, 7-55
SYSFAULT, 7-55
System block diagram, 1-2
System Data Error bit, 7-55
System fatal errors, I/O port, 6-66
System Fault bit, 7-55
System interleave, 4-15
System Pipe Disable bit, 7-52
SYS_PIPE_DIS, 7-52
T
Tags
B-cache, 4-3
TCE, 7-27
TDE, 7-28
TIOP_SEL, 3-12
TLBER register, 7-7
TLCNR register, 7-14
TLCONxx registers, 7-69
TLCON register, 7-68
TLCPUMASK register, 7-31
TLDEV register, 7-5
TLDIAG register, 7-47
TLDMADRA register, 7-75
TLDMADRB register, 7-76
TLDMCMD register, 7-72
TLDTAGDATA register, 7-50
TLDTAGSTAT register, 7-51
TLEPAERR register, 7-54
TLEPDERR register, 7-57
Index-11

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