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Table 7-48 MDRA Register Bit Definitions (Continued)
Name
Bit(s)
1
<6>
POEM
<5>
FRUN
<4>
EXST
<3>
MMPS
1 Lock on Error (LOE) in the four Data Diagnostic Registers (DDR0:3) must be set prior to executing self-test in POEM
mode. This ensures that the Self-Test Data Error registers capture the first failure only.
2 If the SRAM option is selected (NVRAM memory option), <EXST> is not set and self-test is not be executed under any
circumstance.
7-100 System Registers
Type
Function
R/W, 01
Pause on Error Mode. When set, self-test will
halt execution upon the detection of a data mis-
match error. TLSB_DATA_ERROR is asserted
and remains asserted providing that <DEDA> is
cleared, until either <POEM> is set or the mod-
ule is reset. This bit is used in conjunction with
<EXST> to execute self-test in this mode. When
set, self-test continues to loop until <EXST> is
cleared by software, when TLSB_RESET is as-
serted or <NRST> is set.
R/W, 0
Free Run. When set in conjunction with
<EXST>, memory will continue to loop on self-
test until <EXST> is cleared, TLSB_RESET is
asserted, or Node Reset is asserted. If while op-
erating in Free Run mode, self-test detects a
data mismatch, TLSB_DATA_ERROR will as-
sert and remain asserted providing that DEDA
is cleared, until either FRUN is cleared or the
module is reset. Setting this bit in conjunction
with other self-test modes results in Undefined
operations.
R/W, 1
Execute Self-Test. When set, and the DRAM
option mode is selected, memory self-test is in-
voked. The self-test logic examines this bit and
bits <10:9> in MCR to determine if self-test
should be executed. If the option field is zero,
self-test does not execute. This bit is set
system power-up or TLSB_RESET.
R/W, 0
Moving Inversion Pattern Select. When set,
memory self-test executes a specific moving in-
version test pattern that combines specific data
and address test patterns known to detect
DRAM sensitivity faults. This bit must be se-
lected in conjunction with bit <3> (Self-Test Pat-
tern Select) in DDR0:3 registers to execute this
special test. This mode is normally selected only
during memory manufacturing.
2
upon
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