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The I/O port can support up to 16 CPU chips. However, if more than four
CPU chips are present, any additional CPU chip must share a TLMBPR
register pair with another CPU chip.
CAUTION: If two CPUs are sharing a common TLMBPR, there is a slight possibility
that one of the CPUs could continually win access to that TLMBPR, thus
causing the other CPU to be locked out of ever gaining access to it.
The Mailbox Command packet contains the I/O command, I/O target ad-
dress, and data/mask to be written if the command is a write. If the com-
mand is not a write, the data/mask field is I/O adapter implementation de-
pendent (that is, XMI or Futurebus+). The actual command (for example,
CSR write, CSR read) is contained in the CMD<31:0> field of the packet.
After the Mailbox Command packet is sent down the hose, the I/O bus
adapter module executes the decoded mailbox command over the target I/O
bus (XMI or Futurebus+). Status for the successful or unsuccessful
mailbox command is returned to the I/O port through a Mailbox Status Re-
turn packet.
Upon receiving the Mailbox Status Return packet from the I/O adapter
module, the I/O port executes a Read-Modify-Write operation on the TLSB
bus to fetch the mailbox structure, merge the information from the
Mailbox Status Return packet, and write the results back to main memory.
The Read-Modify-Write operation requires one TLSB bus Read Bank Lock
transaction followed by one TLSB bus Write Bank Unlock transaction.
First, the I/O port executes a Read Bank Lock to the mailbox structure in
TLSB memory. When the mailbox data is returned, it is merged with the
information from the Mailbox Status Return packet and written back to
memory.
The information from the Mailbox Status Return packet that is merged
into the mailbox structure includes return data (if the mailbox transaction
was a read), a device specific field, an error bit if an error was detected,
and a done bit. If the mailbox transaction was not a read, the return data
field is Unpredictable.
If the I/O port is node 8, the data is written back immediately using the
highest priority arbitration ID (TLSB_REQ8_HIGH) to minimize latency.
If the I/O port is not node 8, it uses TLSB_REQ<n>, where n is the node
number. Atomicity is guaranteed by the Read Bank Lock/Write Bank Un-
lock TLSB commands.
If an error is detected by the I/O adapter module during a mailbox transac-
tion, the Mailbox Status Return packet on the Up Hose will have the error
bit set. If the error occurred during a mailbox transaction that was a
write, the I/O adapter module may also send an INTR/IDENT packet over
the Up Hose to notify the appropriate CPU(s). If the error occurred during
a mailbox transaction that was a read, the I/O adapter module may return
an error code in the device specific field. The I/O port merges this data
back into the mailbox structure in TLSB memory, and the CPU reads the
mailbox structure to detect the error. The read return data is Unpredict-
able.
NOTE: The specific response of the I/O adapter is implementation dependent.
If the I/O port detects an error during a mailbox transaction, it logs the er-
ror and generates an error interrupt to the appropriate CPU(s).
6-6 I/O Port
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