DEC AlphaServer 8200 Technical Manual page 380

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CPU Module Configuration, 7-52
Data Diagnostic, 7-106
Data Mover Command, 7-72
Data Mover Destination Address, 7-76
Data Mover Source Address, 7-75
Diagnostic Setup, 7-47
DIGA Communications Test, 7-69
DIGA Error, 7-57
DTag Data, 7-50
DTag Status, 7-51
GBUS$LED, 7-78
GBUS$MISCR, 7-79
GBUS$MISCW, 7-81
GBUS$SERNUM, 7-83
GBUS$TLSBRST, 7-82
GBUS$WHAMI, 7-77
Information Base Repair, 7-140
Interrupt Mask, 7-63
Interrupt Source, 7-65
I/O Control Chip Diagnostic, 7-122
I/O Control Chip Mode Select, 7-112
I/O Control Chip Node-Specific Error, 7-117
I/O Ctrl Chip Mailbox Transaction, 7-125
I/O Ctrl Chip Window Transaction, 7-127
I/O Data Path Diagnostic, 7-133
I/O Data Path Mode Select, 7-138
I/O Data Path Node Specific Error, 7-128
I/O Data Path Vector, 7-137
Memory Configuration, 7-89
Memory Diagnostic A, 7-98
Memory Diagnostic B, 7-102
Memory Error, 7-97
Memory Interleave, 7-87
Memory Channel Range, 7-70
MMG Error, 7-59
Reflective Memory Range, 7-110
Self-Test Address Isolation, 7-93
Self-Test Data Error, 7-103
Self-Test Error, 7-95
Serial EEPROM Control/Data, 7-86
TLRMDQRX, 7-39
TLRMDQR8, 7-40
Voltage Margining, 7-62
Registers
Error Syndrome, 7-26
Ethernet, 7-142
Failing Address, 7-24
FDDI, 7-142
ITIOP specific, 7-142
I/O port specific, 7-109
Mailbox Pointer, 7-32
Memory Mapping, 7-21
memory specific, 7-85
NVRAM, 7-142
PCIA, 7-142
PCI device, 7-142
Index-10
SCSI, 7-142
TLBER, 7-7
TLCNR, 7-14
TLDEV, 7-5
TLILID0-3, 7-30
TLIOINTR4-8, 7-36
TLIPINTR, 7-35
TLMCR, 7-43
TLRDRD, 7-41
TLRDRE, 7-42
TLVID, 7-19
TLWSDQR4-8, 7-38
Registers, CPU module, 7-44, 7-45
Registers, Gbus, 7-46
Register access acronyms, 7-2
Register address mapping, 7-2
Register conventions, 7-1
Register list, TLSB, 7-4
Remote bridge access, 7-33
Remote bus address, 7-33
Remote bus command, 7-33
Remote bus interrupts, 6-8
Remote I/O access, 6-14
REQDE, 7-10
Request assertion, 2-13
Request Deassertion Error bit, 7-10
Request Transmit Check Error bit, 7-11
Reset Status bit, 7-15
RFR, 7-99
RMRR registers, 7-110
RM Interleave Enable bit, 7-71
RM_INTLV, 7-73
RM_RANGE_xx registers, 7-70
RM_SIZE, 7-53
RM_3, 7-73
RM_4, 7-73
ROM-based diagnostics, 1-7
RSTSTAT, 7-15, 7-60
RTCE, 7-11
S
SBANK, 7-21
SCLK, 7-86, 7-141
SCSI ports, 6-82
SCSI registers, 7-142
Second Correctable Write Data Error bit, 7-9
Second-level cache, 4-2
SECR register, 7-86
Self-Test Address Isolation register, 7-93
Self-Test Data Error register, 7-103
Self-Test Data Error Register_A bits, 7-104
Self-Test Data Error Register_B bits, 7-104
Self-Test Data Error Register_C bits, 7-104
Self-Test Data Error Register_D bits, 7-104
Self-Test Data Error Register_E bits, 7-105

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