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Table 7-56 ICCNSE Register Bit Definitions (Continued)
Name
MULT_INTR_ERR
UP_HDR_IE
UP_HOSE_PAR_ERR
7-120 System Registers
Bit(s)
Type
Function
<22>
W1C, 0
Multiple Interrupt Error. The I/O port has
four TLILID FIFOs, one for each IPL. Each
TLILID FIFO is four entries deep, so it can ac-
cept up to four pending interrupts for the given
IPL level. The MULT_INTR_ERROR bit is set
if a TLILID FIFO overflows. The overflow only
occurs if an I/O adapter module issues multiple
interrupts at a given IPL and the I/O adapter
modules on the other three hoses have inter-
rupts pending at the same IPL (that is, the I/O
port received five interrupts from the hoses at
a given IPL before the CPU read the TLILID
for the first interrupt).
An IPL17 interrupt is generated when these
bits set if interrupts are enabled by
INTR_NSES (ICCNSE<31>).
<21:20>
W1C, 0
Up HDR Internal Error. A bit set in this
field indicates that one of the two Up HDR gate
arrays detected an illogical internal error. The
internal error generally indicates a hardware
problem where control logic encountered an
undefined condition or conditions.
An IPL 17 interrupt is generated when these
bits set if interrupts are enabled by
INTR_NSES (ICCNSE<31>). The I/O port
should be reset if this error bit is set.
<19:16>
W1C, 0
Up Hose Parity Error. This field indicates
that one of the Up HDR gate arrays detected a
parity error on either the command or data cy-
cles for the corresponding Up Hose.
An IPL 17 interrupt is generated when these
bits set if interrupts are enabled by INTR_
NSES (ICCNSE<31>).
UP_HDR_IE<1> detects errors in Up-
HDR-HDR-B (hose<3:2>)
UP_HDR_IE<0> detects errors in Up-
HDR-HDR-A (hose<1:0>)
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