Scsi Ports - DEC AlphaServer 8200 Technical Manual

The PCI interface consists of the following sections:
These sections are discussed below.
HPC Gate Arrays
Each HPC provides the connection between the internal hose and each
PCI bus (PCI0 and PCI1).
The HPCs provide access to all three PCI address spaces: memory space,
I/O space, and configuration space. All three are accessible using sparse
address mapping that allows for individual byte access. PCI memory space
is also accessible through dense mapping, which supports cache block-sized
bursts. PCI memory and I/O space each appear as a contiguous 32-bit ad-
dress space across both PCI buses. Accesses to these address spaces are
sent to both buses. PCI configuration space is contiguous across both
buses but accesses are only sent to one bus.
Map RAM
The integrated I/O port supports 128 Kbytes of scatter/gather (32K-entry)
map RAM. The map RAM, when enabled, is used to store the page entry
used to form the 40-bit system memory address. The map RAM is accessi-
ble through the HPC gate array.
NOTE: All Map RAM locations must be written to before reading to set correct par-
ity.
Control Logic
The hose control logic consists of:
6.8.1.2

SCSI Ports

The KFTIA module supports:
The single-ended SCSI port supports the fast synchronous transfer mode
with a bandwidth of 10 Mbyte/sec, and the differential SCSI ports support
the fast synchronous transfer mode with a bandwidth of 20 Mbyte/sec. The
single-ended SCSI port uses the SCSI-2 50-pin high-density connector and
is optionally (software controlled) terminated internally on the integrated
I/O port using an active SCSI terminator. The differential ports use the
68-pin high-density connector and are not terminated internally on the in-
tegrated I/O port. Two of the SCSI ports are on PCI0, and the other two
are on PCI1.
6-82 I/O Port
• Two HPC (hose to PCI) gate arrays
• Map RAM
• Up Hose control logic
• Up Hose control PAL
• Map RAM control PAL
• One 8-bit single-ended SCSI port
• Three 16-bit differential SCSI ports