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Table 7-22 TLDIAG Register Bit Definitions (Continued)
Name
Bit(s)
<1>
DTWR
<0>
FRIGN
Type
Function
W, 0
DTag Write. When set, causes the DTag entry at the in-
dex specified by the next memory space read to be writ-
ten with the value in the TLDTAGDATA and TLDTAG-
STAT registers. The entry is written to the CPU specified
by <DTCP>. Valid only when <FRIGN> is set.
R/W, 1
Force Ignore. When set, causes all TLSB transactions
to be ignored and disallows transactions from this mod-
ule to go to the TLSB. Causes the module to drop out of
the distributed arbitration scheme. <FRIGN> causes
transactions from this module to be bypassed to the bus
interface inputs without going to the bus. Note that al-
though this bit can be read, the value is read from the
copy in the DIGA chip (CPU module). Several copies of
<FRIGN> are distributed to all the control arrays.
System Registers 7-49
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