Table of Contents
Advertisement
2-7
TLSB Node Base Addresses ....................................................................................... 2-28
2-8
TLSB CSR Address Mapping ..................................................................................... 2-29
2-9
Mailbox Data Structure .............................................................................................. 2-31
2-10
Address Bus Error Summary ..................................................................................... 2-39
2-11
Signals Covered by TLESRn Registers ...................................................................... 2-39
2-12
Data Bus Error Summary .......................................................................................... 2-42
3-1
Directly Addressable Console Hardware ..................................................................... 3-6
3-2
TLSB Wrapping ........................................................................................................... 3-7
3-3
CPU Module Wrapping ................................................................................................ 3-7
3-4
Decrement Queue Counter Address Assignments .................................................... 3-11
3-5
PCI Address Bit Descriptions ..................................................................................... 3-12
3-6
4-1
B-Cache States .............................................................................................................. 4-5
4-2
State Transition Due to Processor Activity ................................................................. 4-7
4-3
State Transition Due to TLSB Activity ....................................................................... 4-8
4-4
CPU Module Response to Lock Register and Victim Buffer Address Hits ................ 4-8
4-5
Memory Array Capacity ............................................................................................. 4-13
4-6
Self-Test Error Registers ............................................................................................ 4-18
4-7
Self-Test Times: Normal Mode ................................................................................... 4-19
4-8
Self-Test Times: Moving Inversion, No Errors Found .............................................. 4-20
5-1
TLSB Command Encoding ........................................................................................... 5-3
5-2
Two Strings-128MB/512MB Row/Column Address Bit Swapping ........................... 5-6
5-3
Four Strings-256MB/1024MB Row/Column Address Bit Swapping ........................ 5-7
5-4
Eight Strings-512MB/2048MB Row/Column Address Bit Swapping ...................... 5-8
5-5
Error Conditions Monitored by the MDIs .................................................................. 5-12
5-6
CSRCA Addressing ..................................................................................................... 5-15
5-7
CSRCA Data Bus Master ........................................................................................... 5-17
6-1
I/O Port Transaction Types .......................................................................................... 6-5
6-2
TLMBPR Register Map .............................................................................................. 6-15
6-3
Sparse Address Space Read Field Descriptions ........................................................ 6-17
6-4
Sparse Address Space Write Field Descriptions ....................................................... 6-19
6-5
Sparse Address Write Length Encoding .................................................................... 6-20
6-6
Dense Address Space Transaction Field Descriptions .............................................. 6-21
6-7
Transaction Types Supported by the I/O Port ........................................................... 6-24
6-8
Wrapped Reads ........................................................................................................... 6-25
6-9
I/O Adapter to Memory Write Types .......................................................................... 6-26
6-10
Down Hose Signals ..................................................................................................... 6-38
6-11
Up Hose Signals .......................................................................................................... 6-38
6-12
UPCTL<3:0> Encoding ............................................................................................... 6-39
6-13
Hose Status Signals .................................................................................................... 6-40
6-14
Down Hose Packet Type Codes .................................................................................. 6-40
6-15
Mailbox Command Packet Description ...................................................................... 6-42
6-16
DMA Read Data Return Packet Description ............................................................. 6-43
6-17
DMA Read Data Return Packet with Error Description .......................................... 6-44
6-18
INTR/IDENT Status Return Packet Description ...................................................... 6-45
6-19
Sparse Window Read Command Packet Description ................................................ 6-46
6-20
Sparse Window Write Command Packet Description ............................................... 6-48
6-21
Dense Window Read Command Packet Description ................................................. 6-49
6-22
Dense Window Write Command Packet Description ................................................ 6-51
6-23
Memory Channel Write Packet Description .............................................................. 6-53
6-24
Mailbox Status Return Packet Description ............................................................... 6-54
6-25
DMA Read Packet Description ................................................................................... 6-55
6-26
DMA Read Packet Sizes ............................................................................................. 6-55
6-27
Interlock Read Packet Description ............................................................................. 6-56
6-28
Interlock Read Packet Size ......................................................................................... 6-56
6-29
DMA Masked Write Packet Description .................................................................... 6-58
xii
Advertisement
Table of Contents
