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Table 7-48 MDRA Register Bit Definitions (Continued)
Name
Bit(s)
<2>
FCAPE
<1>
FRAPE
<0>
AMEN
Type
Function
R/W, 0
Force Column Address Parity Error. When
set, incorrect DRAM column address parity is
written into the addressed location when a
match is detected between the TLSB address
and the MDRB register and when <AMEN> is
also set.
R/W, 0
Force Row Address Parity Error. When set,
incorrect DRAM row address parity is written
into the addressed location when a match is de-
tected between the TLSB address and the MDRB
register and when <AMEN> is also set.
R/W, 0
Address Match Enable. When set, a TLSB
memory space address or a self-test generated
address is matched against the 32-bit 64-byte
aligned address contained in MDRB. If a match
is detected, and if bit 15, <EFLPD>, and/or bit
14, <EFLPC>, in one or all of the DDR0:3 regis-
ters are also set, then the data bit and/or check
bit selected to be flipped during a memory space
write will be written to memory inverted. In ad-
dition to the above, AMEN is also used to enable
address match comparisons to force ROW and
COL parity errors.
System Registers 7-101
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