DEC AlphaServer 8200 Technical Manual page 7

5.2.2.3 CSR Write Data ECC Check ......................................................................... 5-10
5.2.2.4 Forcing Write Errors for Diagnostics ............................................................ 2-15
5.2.2.5 Write Data Out Selection .............................................................................. 2-15
5.2.3 Read Data Output Logic ....................................................................................... 2-16
5.2.3.1 Read Data Buffers .......................................................................................... 2-16
5.2.3.2 Read Data Path ECC Algorithm ................................................................... 5-11
5.2.3.3 CSR Read Data ECC ...................................................................................... 2-17
5.2.4 MDI Error Detection and Correction Logic ......................................................... 2-17
5.3 CSR Interface .............................................................................................................. 5-13
5.3.1 CTL CSR Functions .............................................................................................. 2-18
5.3.1.1 TLSB CSR Control ......................................................................................... 2-18
MAI CSR Sequencer
5.3.1.2
5.3.1.3 CSR Multiplexing ........................................................................................... 2-19
5.3.1.4 CSRCA Parity ................................................................................................ 2-19
5.3.2 MDI CSR Functions ............................................................................................. 2-19
5.3.2.1 MDI CSR Sequencer ...................................................................................... 2-19
5.3.2.2 Merge Register ............................................................................................... 2-20
5.3.2.3 CSR Multiplexing ........................................................................................... 2-20
5.3.2.4 CSRCA Parity ................................................................................................ 2-20
Chapter 6 I/O Port
6.1 Configuration ................................................................................................................ 6-2
6.2 I/O Port Main Components ........................................................................................... 6-2
6.3 I/O Port Transactions ................................................................................................... 6-3
6.3.1 Mailbox Transactions ............................................................................................. 6-5
6.3.2 I/O Window Space Transactions ............................................................................ 6-7
6.3.2.1 CSR Write Transactions to I/O Window Space .............................................. 6-7
6.3.2.2 CSR Read Transactions to I/O Window Space ............................................... 6-8
6.3.3 Interrupt Transactions ........................................................................................... 6-8
6.3.3.1 Remote Bus Interrupts .................................................................................... 6-8
6.3.3.2 I/O Port Generated Error Interrupts .............................................................. 6-9
6.3.4 DMA Read Transactions ...................................................................................... 6-10
6.3.5 DMA Interlock Read Transactions ...................................................................... 6-10
6.3.6 DMA Write Transactions ..................................................................................... 6-11
6.3.6.1 DMA Unmasked Write .................................................................................. 6-12
6.3.6.2 DMA Masked Write Request to Memory ...................................................... 6-12
6.3.7 Extended NVRAM Write Transactions ............................................................... 6-13
6.4 Addressing ................................................................................................................... 6-14
6.4.1 Accessing Remote I/O Node CSRs Through Mailboxes ...................................... 6-14
6.4.2 Accessing Remote I/O Node CSRs Through Direct I/O Window Space ............. 6-15
6.4.2.1 Sparse Address Space Reads ......................................................................... 6-15
6.4.2.2 Sparse Address Space Writes ........................................................................ 6-17
6.4.3 Dense Address Space Transactions ..................................................................... 6-20
6.5 TLSB Interface ............................................................................................................ 6-23
6.5.1 Transactions ......................................................................................................... 6-23
6.5.1.1 DMA Transactions ......................................................................................... 6-24
6.5.1.2 Interrupt Transactions ................................................................................. 6-26
6.5.1.3 CSR Transactions .......................................................................................... 6-28
6.5.2 TLSB Arbitration .................................................................................................. 6-30
6.5.2.1 Node 8 I/O Port Arbitration Mode Selection ................................................. 6-31
6.5.2.2 Read-Modify-Write ......................................................................................... 6-33
6.5.2.3 Bank Collision Effect on Priority .................................................................. 6-34
6.5.2.4 Look-Back-Two ............................................................................................... 6-34
6.5.2.5 Arbitration Suppress ..................................................................................... 6-34
............................................................................... 5-15
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