DEC AlphaServer 8200 Technical Manual page 8

6.5.3 Error Detection Schemes ..................................................................................... 6-34
6.6 Hose Interface ............................................................................................................. 6-35
6.6.1 Hose Protocol ....................................................................................................... 6-35
6.6.2 Window Space Mapping ....................................................................................... 6-36
6.6.2.1 Sparse Address Mapping ............................................................................... 6-37
6.6.2.2 Dense Address Mapping ................................................................................ 6-37
6.6.3 Hose Signals ......................................................................................................... 6-37
6.6.4 Hose Packet Specifications ................................................................................... 6-39
6.6.4.1 Down Hose Packet Specifications ................................................................. 6-39
6.6.4.2 Up Hose Packet Specifications ...................................................................... 6-52
6.6.5 Hose Errors ........................................................................................................... 6-65
6.7 I/O Port Error Handling ............................................................................................. 6-66
6.7.1 Soft TLSB Errors Recovered by Hardware ......................................................... 6-66
6.7.2 Hard TLSB Errors ................................................................................................ 6-66
6.7.3 System Fatal Errors ............................................................................................. 6-66
6.7.4 Hard Internal I/O Port Errors ............................................................................. 6-66
6.7.5 Error Reporting .................................................................................................... 6-67
6.7.5.1 TLSB_DATA_ERROR .................................................................................... 6-67
6.7.5.2 TLSB_FAULT ................................................................................................ 6-68
6.7.6 IPL 17 Error Interrupts ....................................................................................... 6-69
6.7.7 Address Bus Errors .............................................................................................. 6-70
6.7.7.1 TLSB Address Transmit Check Errors ......................................................... 6-70
6.7.7.2 Address Bus Parity Errors ............................................................................ 6-71
6.7.7.3 No Acknowledge Errors ................................................................................. 6-71
6.7.7.4 Unexpected Acknowledge .............................................................................. 6-71
6.7.7.5 Bank Busy Violation ...................................................................................... 6-71
6.7.7.6 Memory Mapping Register Error .................................................................. 6-71
6.7.8 Data Bus Errors .................................................................................................... 6-72
6.7.8.1 Single-Bit ECC Errors ................................................................................... 6-72
6.7.8.2 Double-Bit ECC Errors .................................................................................. 6-72
6.7.8.3 Illegal Sequence Errors .................................................................................. 6-73
6.7.8.4 SEND_DATA Timeout Errors ....................................................................... 6-73
6.7.8.5 Data Status Errors ......................................................................................... 6-73
6.7.8.6 Transmit Check Errors .................................................................................. 6-74
6.7.8.7 Multiple Data Bus Errors .............................................................................. 6-74
6.7.9 Additional TLSB Status ....................................................................................... 6-74
6.7.10 Hard I/O Port Errors ............................................................................................ 6-75
6.7.10.1 Up Hose Errors ............................................................................................... 6-75
6.7.10.2 Up Turbo Vortex Errors ................................................................................ 6-75
6.7.10.3 Down Turbo Vortex Errors ............................................................................ 6-76
6.7.11 Miscellaneous I/O Port Errors ............................................................................. 6-77
6.7.11.1 CSR Bus Parity Errors .................................................................................. 6-77
6.7.11.2 Unexpected Mailbox Status Packet .............................................................. 6-77
6.7.11.3 ICR and IDR Internal Illogical Errors .......................................................... 6-77
6.7.11.4 Hose Status Change Errors ........................................................................... 6-78
6.8 KFTIA Overview ......................................................................................................... 6-78
6.8.1 Integrated I/O Section ......................................................................................... 6-80
6.8.1.1 PCI Interface .................................................................................................. 6-81
6.8.1.2 SCSI Ports ..................................................................................................... 6-82
6.8.1.3 Ethernet Ports ................................................................................................ 6-83
6.8.1.4 Optional NVRAM Daughter Card ................................................................ 6-83
6.8.2 Integrated I/O Section Transactions ................................................................... 6-83
6.8.2.1 DMA Transactions ......................................................................................... 6-83
6.8.2.2 Mailbox Transaction ...................................................................................... 6-84
6.8.2.3 CSR Transactions ......................................................................................... 6-84
6.8.2.4 Interrupt Transactions .................................................................................. 6-84
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