Clg Interrupt Enable Register - Epson S1C17M20 Technical Manual

2 POWER SUPPLY, RESET, AND CLOCKS
Bit 5 OSC1STPIF
Bit 4 OSC3TEDIF
Bit 2 OSC3STAIF
Bit 1 OSC1STAIF
Bit 0 IOSCSTAIF
These bits indicate the CLG interrupt cause occurrence statuses.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
Each bit corresponds to the interrupt as follows:
CLGINTF.OSC1STPIF bit: OSC1 oscillation stop interrupt
CLGINTF.OSC3TEDIF bit: OSC3 oscillation auto-trimming completion interrupt
CLGINTF.OSC3STAIF bit: OSC3 oscillation stabilization waiting completion interrupt
CLGINTF.OSC1STAIF bit: OSC1 oscillation stabilization waiting completion interrupt
CLGINTF.IOSCSTAIF bit: IOSC oscillation stabilization waiting completion interrupt
Note: The CLGINTF.IOSCSTAIF bit is 0 after system reset is canceled, but IOSCCLK has already
been stabilized.

CLG Interrupt Enable Register

Register name Bit
CLGINTE 15–8 –
7
6
5
4
3
2
1
0
Bits 15–6, 3 Reserved
Bit 5 OSC1STPIE
Bit 4 OSC3TEDIE
Bit 2 OSC3STAIE
Bit 1 OSC1STAIE
Bit 0 IOSCSTAIE
These bits enable the CLG interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Each bit corresponds to the interrupt as follows:
CLGINTE.OSC1STPIE bit: OSC1 oscillation stop interrupt
CLGINTE.OSC3TEDIE bit: OSC3 oscillation auto-trimming completion interrupt
CLGINTE.OSC3STAIE bit: OSC3 oscillation stabilization waiting completion interrupt
CLGINTE.OSC1STAIE bit: OSC1 oscillation stabilization waiting completion interrupt
CLGINTE.IOSCSTAIE bit: IOSC oscillation stabilization waiting completion interrupt
2-20
Bit name Initial
0x00
– 0
(reserved) 0
OSC1STPIE 0
OSC3TEDIE 0
– 0
OSC3STAIE 0
OSC1STAIE 0
IOSCSTAIE 0
Seiko Epson Corporation
Reset R/W
– R –
– R
H0 R
H0 R/W
H0 R/W
– R
H0 R/W
H0 R/W
H0 R/W
S1C17M20/M21/M22/M23/M24/M25
Remarks
TECHNICAL MANUAL (Rev. 1.0)