Clg Interrupt Enable Register; Clg Fout Control Register - Epson S1C17M01 Technical Manual

Bit 1 OSC1STAIF
Bit 0 IOSCSTAIF
These bits indicate the oscillation stabilization waiting completion interrupt cause occurrence status in
each clock source.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
Each bit corresponds to the clock source as follows:
CLGINTF.OSC1STAIF bit: OSC1 oscillator circuit
CLGINTF.IOSCSTAIF bit: IOSC oscillator circuit
Note: The CLGINTF.IOSCSTAIF bit is 0 after system reset is canceled, but IOSCCLK has already
been stabilized.

CLG Interrupt Enable Register

Register name Bit
CLGINTE 15–8 –
7–6 –
5
4
3–2 –
1
0
Bits 15–6 Reserved
Bit 5 OSC1STPIE
Bit 4 IOSCTEDIE
These bits enable the OSC1 oscillation stop and IOSC oscillation auto-trimming completion inter-
rupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Each bit corresponds to the interrupt as follows:
CLGINTE.OSC1STPIE bit: OSC1 oscillation stop interrupt
CLGINTE.IOSCTEDIE bit: IOSC oscillation auto-trimming completion interrupt
Bits 3–2 Reserved
Bit 1 OSC1STAIE
Bit 0 IOSCSTAIE
These bits enable the oscillation stabilization waiting completion interrupt of each clock source.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Each bit corresponds to the clock source as follows:
CLGINTE.OSC1STAIE bit: OSC1 oscillator circuit
CLGINTE.IOSCSTAIE bit: IOSC oscillator circuit

CLG FOUT Control Register

Register name Bit
CLGFOUT 15–8 –
7
6–4 FOUTDIV[2:0]
3–2 FOUTSRC[1:0]
1
0
S1C17M01 TECHNICAL MANUAL
(Rev. 1.2)
Bit name Initial
0x00
0x0
OSC1STPIE 0
IOSCTEDIE 0
0x0
OSC1STAIE 0
IOSCSTAIE 0
Bit name Initial
0x00
– 0
0x0
0x0
– 0
FOUTEN 0
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
Reset R/W
– R –
– R
H0 R/W
H0 R/W
– R
H0 R/W
H0 R/W
Reset R/W
– R –
– R
H0 R/W
H0 R/W
– R
H0 R/W
Remarks
Remarks
2-17