Clg Interrupt Enable Register - Epson S1C31W74 Technical Manual

Bit 8 IOSCTERIF
Bit 5 OSC1STPIF
Bit 4 IOSCTEDIF
Bit 2 OSC3STAIF
Bit 1 OSC1STAIF
Bit 0 IOSCSTAIF
These bits indicate the CLG interrupt cause occurrence statuses.
1 (R): Cause of interrupt occurred
0 (R): No cause of interrupt occurred
1 (W): Clear flag
0 (W): Ineffective
Each bit corresponds to the interrupt as follows:
CLGINTF.IOSCTERIF bit: IOSC oscillation auto-trimming error interrupt
CLGINTF.OSC1STPIF bit: OSC1 oscillation stop interrupt
CLGINTF.IOSCTEDIF bit: IOSC oscillation auto-trimming completion interrupt
CLGINTF.OSC3STAIF bit: OSC3 oscillation stabilization waiting completion interrupt
CLGINTF.OSC1STAIF bit: OSC1 oscillation stabilization waiting completion interrupt
CLGINTF.IOSCSTAIF bit: IOSC oscillation stabilization waiting completion interrupt
Note: The CLGINTF.IOSCSTAIF bit is 0 after system reset is canceled, but IOSCCLK has already
been stabilized.

CLG Interrupt Enable Register

Register name Bit
CLGINTE 15–9 –
8
7
6
5
4
3
2
1
0
Bits 15–9, 7, 6, 3 Reserved
Bit 8 IOSCTERIE
Bit 5 OSC1STPIE
Bit 4 IOSCTEDIE
Bit 2 OSC3STAIE
Bit 1 OSC1STAIE
Bit 0 IOSCSTAIE
These bits enable the OSC1 oscillation stop and IOSC oscillation auto-trimming completion inter-
rupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Each bit corresponds to the interrupt as follows:
CLGINTE.IOSCTERIE bit: IOSC oscillation auto-trimming error interrupt
CLGINTE.OSC1STPIE bit: OSC1 oscillation stop interrupt
CLGINTE.IOSCTEDIE bit: IOSC oscillation auto-trimming completion interrupt
CLGINTE.OSC3STAIE bit: OSC3 oscillation stabilization waiting completion interrupt
CLGINTE.OSC1STAIE bit: OSC1 oscillation stabilization waiting completion interrupt
CLGINTE.IOSCSTAIE bit: IOSC oscillation stabilization waiting completion interrupt
S1C31W74 TECHNICAL MANUAL
(Rev. 1.1)
Bit name Initial
0x00
IOSCTERIE 0
– 0
(reserved) 0
OSC1STPIE 0
IOSCTEDIE 0
– 0
OSC3STAIE 0
OSC1STAIE 0
IOSCSTAIE 0
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
Reset R/W
– R –
H0 R/W
– R
H0 R
H0 R/W
H0 R/W
– R
H0 R/W
H0 R/W
H0 R/W
Remarks
2-21