Epson S1C17M20 Technical Manual page 33

2 POWER SUPPLY, RESET, AND CLOCKS
5. Write a value other than 0x0096 to the MSCPROT.PROT[15:0] bits. (Set system protection)
6. When using the crystal/ceramic oscillator, assign the OSC3 oscillator input/output functions to the ports.
(Refer to the "I/O Ports" chapter.)
7. Write 1 to the CLGOSC.OSC3EN bit.
8. OSC3CLK can be used if the CLGINTF.OSC3STAIF bit = 1 after an interrupt occurs.
The setting values of the CLGOSC3.OSC3INV[1:0] and CLGOSC3.OSC3WT[2:0] bits should be determined
after performing evaluation using the populated circuit board.
Note: Make sure the CLGOSC.OSC3EN bit is set to 0 (while the OSC3 oscillation is halted) when
switching the oscillator within two types.
System clock switching
The CPU boots using IOSCCLK as SYSCLK. After booting, the clock source of SYSCLK can be switched ac-
cording to the processing speed required. The SYSCLK frequency can also be set by selecting the clock source
division ratio, this makes it possible to run the CPU at the most suitable performance for the process to be ex-
ecuted. The CLGSCLK.CLKSRC[1:0] and CLGSCLK.CLKDIV[1:0] bits are used for this control.
The CLGSCLK register bits are protected against writings by the system protect function, therefore, the system
protection must be removed by writing 0x0096 to the MSCPROT.PROT[15:0] bits before the register setting can
be altered. For the transition between the operating modes including the system clock switching, refer to "Oper-
ating Mode."
Clock control in SLEEP mode
The CPU enters SLEEP mode when it executes the slp instruction. Whether the clock sources being operated
are stopped or not at this point can be selected in each source individually. This allows the CPU to fast switch
between SLEEP mode and RUN mode, and the peripheral circuits to continue operating without disabling
the clock in SLEEP mode. The CLGOSC.IOSCSLPC, CLGOSC.OSC1SLPC, CLGOSC.OSC3SLPC, and
CLGOSC.EXOSCSLPC bits are used for this control. Figure 2.3.4.3 shows a control example.
(1) When the CLGOSC.OSC1SLPC bit = 1
SYSCLK
(CPU operating clock)
RTCA
operating clock
(2) When the CLGOSC.OSC1SLPC bit = 0
SYSCLK
(CPU operating clock)
RTCA
operating clock
The SYSCLK condition (clock source and division ratio) at wake-up from SLEEP mode to RUN mode can also
be configured. This allows flexible clock control according to the wake-up process. Configure the clock using
the CLGSCLK.WUPSRC[1:0] and CLGSCLK.WUPDIV[1:0] bits, and write 1 to the CLGSCLK.WUPMD bit
to enable this function.
2-10
SLEEP mode
IOSCCLK
(CPU stop, CLK stop)
Executing the
slp instruction
(CLK stop)
OSC1CLK
∗ The RTCA stops counting in
SLEEP mode as the clock stops.
SLEEP mode
IOSCCLK
(CPU stop, CLK stop)
Executing the
slp instruction
∗ The RTCA continues counting in
SLEEP mode as the clock is being supplied.
Figure 2.3.4.3 Clock Control Example in SLEEP Mode
Seiko Epson Corporation
(Start oscillation)
Oscillation stabilization waiting time
IOSCCLK
(Unstable)
Interrupt
(Wake-up)
OSC1CLK
(Unstable)
IOSCCLK
(Unstable)
Interrupt
(Wake-up)
OSC1CLK
S1C17M20/M21/M22/M23/M24/M25
IOSCCLK
OSC1CLK
IOSCCLK
TECHNICAL MANUAL (Rev. 1.0)