Block Diagram - Epson S1C17M20 Technical Manual

1.2 Block Diagram

DCLK
DSIO
DST2
System clock
Clock generator
(CLG)
IOSC
FOUT
oscillator
∗
OSC1 OSC1
OSC2 oscillator
OSC3
OSC3
oscillator
OSC4
EXOSC
EXOSC
input circuit
System reset controller
(SRC)
Power-on reset
(POR)
#RESET
Brownout reset
(BOR)
V
DD
Power generator
V
SS
(PWG)
V
D1
* The pin configuration and peripheral circuit function depends on the model. For detailed information, refer to Section 1.3, "Pins."
Figure 1.2.1 S1C17M20/M21/M22/M23/M24/M25 Block Diagram
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
CPU core & debugger
(S1C17)
Interrupt request
16-bit internal bus
Interrupt signal
Interrupt
controller
(ITC)
I/O port
(PPORT)
Watchdog timer
(WDT2)
Real-time clock
(RTCA)
Supply voltage
detector
(SVD3)
16-bit timer
(T16)
4 Ch.
16-bit PWM timer
(T16B)
2Ch.
Seiko Epson Corporation
Multiplier/divider
Coprocessor bus
(COPRO2)
Internal RAM
32-bit RAM bus
2KB
Flash memory
16KB (M20/M21/M22)
Instruction bus
32KB (M23/M24/M25)
∗
P00–07
P10–17
P20–27
P30–37
P40–42
PD0–D1
PD2
∗
PD3–D4
RTC1S
EXSVD0
TOUT00–01
TOUT10–11
CAP00–01
CAP10–11
EXCL00–01
EXCL10–11
1 OVERVIEW
Flash
programming
V
PP
voltage booster
UART
USIN0–1
(UART3)
USOUT0–1
2 Ch.
Synchronous
SDI0–1
serial interface
SDO0–1
(SPIA)
SPICLK0–1
2 Ch.
#SPISS0–1
2
I C
SDA0
(I2C)
SCL0
1 Ch.
Sound generator BZOUT
(SNDA) #BZOUT
IR remote
REMO
controller
CLPLS
(REMC3)
RFIN0–1
R/F converter
REF0–1
(RFC)
SENA0–1
2 Ch.
SENB0–1
12-bit A/D
#ADTRG0
converter
ADIN00–07
(ADC12A)
VREFA0
1 Ch.
∗
∗
1-3