P Port Clock Control Register - Epson S1C17M20 Technical Manual

6 I/O PORTS (PPORT)
This selection takes effect when the PxMODSEL.PxSELy bit = 1.

P Port Clock Control Register

Register name Bit
PCLK 15–9 –
8
7–4 CLKDIV[3:0]
3–2 KRSTCFG[1:0]
1–0 CLKSRC[1:0]
Bits 15–9 Reserved
Bit 8 DBRUN
This bit sets whether the PPORT operating clock is supplied in DEBUG mode or not.
1 (R/WP): Clock supplied in DEBUG mode
0 (R/WP): No clock supplied in DEBUG mode
Bits 7–4 CLKDIV[3:0]
These bits select the division ratio of the PPORT operating clock (chattering filter clock).
Bits 3–2 KRSTCFG[1:0]
These bits configure the key-entry reset function.
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of PPORT (chattering filter).
The PPORT operating clock should be configured by selecting the clock source using the PCLK.
CLKSRC[1:0] bits and the clock division ratio using the PCLK.CLKDIV[3:0] bits as shown in Table
6.6.3. These settings determine the input sampling time of the chattering filter.
6-10
Table 6.6.1 Selecting Peripheral I/O Function
PxFNCSEL.PxyMUX[1:0] bits
0x3
0x2
0x1
0x0
Bit name Initial
0x00
DBRUN
0x0
0x0
0x0
Table 6.6.2 Key-Entry Reset Function Settings
PCLK.KRSTCFG[1:0] bits
0x3
0x2
0x1
0x0
Seiko Epson Corporation
Peripheral I/O function
Function 3
Function 2
Function 1
Function 0
Reset R/W
– R –
0 H0 R/WP
H0 R/WP
H0 R/WP
H0 R/WP
key-entry reset
Reset when P0[3:0] inputs = all low
Reset when P0[2:0] inputs = all low
Reset when P0[1:0] inputs = all low
Disable
Remarks
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)