Clg Interrupt Enable Register; Clg Fout Control Register - Epson S1C17F13 Technical Manual

Each bit corresponds to the clock source as follows:
CLGINTF.OSC3ASTAIF bit: OSC3A oscillator circuit
CLGINTF.OSC1STAIF bit: OSC1 oscillator circuit
CLGINTF.OSC3BSTAIF bit: OSC3B oscillator circuit
Note: The CLGINTF.OSC3BSTAIF bit is 0 after system reset is canceled, but OSC3BCLK has al-
ready been stabilized.

ClG interrupt enable Register

Register name Bit
CLGINTE 15–8 –
7–3 –
2
1
0
Bits 15–3 Reserved
Bit 2 OSC3aSTaie
Bit 1 OSC1STaie
Bit 0 OSC3BSTaie
These bits enable the oscillation stabilization waiting completion interrupt of each clock source.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Each bit corresponds to the clock source as follows:
CLGINTE.OSC3ASTAIE bit: OSC3A oscillator circuit
CLGINTE.OSC1STAIE bit:
CLGINTE.OSC3BSTAIE bit: OSC3B oscillator circuit

ClG FOuT Control Register

Register name Bit
CLGFOUT 15–8 –
7
6–4 FOUTDIV[2:0]
3–2 FOUTSRC[1:0]
1
0
Bits 15–7 Reserved
Bits 6–4 FOuTDiV[2:0]
These bits set the FOUT clock division ratio.
Bits 3–2 FOuTSRC[1:0]
These bits select the FOUT clock source.
CLGFOUT.
FOUTDIV[2:0] bits
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
S1C17F13 TeChniCal Manual
(Rev. 1.0)
Bit name Initial
0x00
0x0
OSC3ASTAIE 0
OSC1STAIE 0
OSC3BSTAIE 0
OSC1 oscillator circuit
Bit name Initial
0x00
– 0
0x0
0x0
– 0
FOUTEN 0
Table 2. 6.8 FOUT Clock Source and Division Ratio Settings
0x0
OSC3BCLK
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
Seiko epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
Reset R/W
– R –
– R
H0 R/W
H0 R/W
H0 R/W
Reset R/W
– R –
– R
H0 R/W
H0 R/W
– R
H0 R/W
CLGFOUT.FOUTSRC[1:0] bits
0x1 0x2
OSC1CLK OSC3ACLK
1/32,768 1/128
1/4,096 1/64
1/1,024 1/32
1/256 1/16
1/8 1/8
1/4 1/4
1/2 1/2
1/1 1/1
Remarks
Remarks
0x3
SYSCLK
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1/1
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