Clock Generator (Clg); Overview - Epson S1C17M20 Technical Manual

2 POWER SUPPLY, RESET, AND CLOCKS
Reset group
H0
H1
S0

2.3 Clock Generator (CLG)

2.3.1 Overview

CLG is the clock generator that controls the clock sources and manages clock supply to the CPU and the peripheral
circuits. The main features of CLG are outlined below.
• Supports multiple clock sources.
- IOSC oscillator circuit that oscillates with a fast startup and no external parts required
- Low-power OSC1 oscillator circuit in which the oscillator type can be specified from high-precision 32.768
kHz crystal oscillator (an external resonator is required) and internal oscillator
- High-speed OSC3 oscillator circuit in which the oscillator type can be specified from crystal/ceramic oscilla-
tor (an external resonator is required) and internal oscillator
- EXOSC clock input circuit that allows input of square wave and sine wave clock signals
• The system clock (SYSCLK), which is used as the operating clock for the CPU and bus, and the peripheral cir-
cuit operating clocks can be configured individually by selecting the suitable clock source and division ratio.
• IOSCCLK output from the IOSC oscillator circuit is used as the boot clock for fast booting.
• Controls the oscillator and clock input circuits to enable/disable according to the operating mode, RUN or
SLEEP mode.
• Provides a flexible system clock switching function at SLEEP mode cancelation.
- The clock sources to be stopped in SLEEP mode can be selected.
- SYSCLK to be used at SLEEP mode cancelation can be selected from all clock sources.
- The oscillator and clock input circuit on/off state can be maintained or changed at SLEEP mode cancelation.
• Provides the FOUT function to output an internal clock for driving external ICs or for monitoring the internal state.
Figure 2.3.1.1 shows the CLG configuration.
Table 2.3.1.1 CLG Configuration of S1C17M20/M21/M22/M23/M24/M25
Item
IOSC oscillator circuit
OSC1 crystal oscillator circuit
OSC1 internal oscillator circuit
OSC3 crystal/ceramic oscillator circuit
OSC3 internal oscillator circuit
EXOSC clock input
2-4
Table 2.2.4.1 List of Reset Groups
Reset source
#RESET pin
POR and BOR
Key-entry reset
Supply voltage detector reset
Watchdog timer reset
#RESET pin
POR and BOR
Peripheral circuit software reset
(MODEN and SFTRST bits. The
software reset operations de-
pend on the peripheral circuit.
S1C17M20/M23
24-pin package
Available
Unavailable
Available
Unavailable
Available
Available
Seiko Epson Corporation
Reset cancelation timing
Reset state is maintained for the reset
hold time t after the reset request is
RSTR
canceled.
Reset state is canceled immediately
after the reset request is canceled.
S1C17M21/M22/M24/M25
32-pin package
Available
Available
Available
Available
Available
Available
S1C17M20/M21/M22/M23/M24/M25
Available
Available
Available
Available
Available
Available
TECHNICAL MANUAL (Rev. 1.0)