Synchronous Serial Interface (Spia); Overview - Epson S1C17M20 Technical Manual

13 Synchronous Serial Interface (SPIA)

13.1 Overview

SPIA is a synchronous serial interface. The features of SPIA are listed below.
• Supports both master and slave modes.
• Data length: 2 to 16 bits programmable
• Either MSB first or LSB first can be selected for the data format.
• Clock phase and polarity are configurable.
• Supports full-duplex communications.
• Includes separated transmit data buffer and receive data buffer registers.
• Can generate receive buffer full, transmit buffer empty, end of transmission, and overrun interrupts.
• Master mode allows use of a 16-bit timer to set baud rate.
• Slave mode is capable of being operated with the external input clock SPICLKn only.
• Slave mode is capable of being operated in SLEEP mode allowing wake-up by an SPIA interrupt.
• Input pins can be pulled up/down with an internal resistor.
Figure 13.1.1 shows the SPIA configuration.
Table 13.1.1 SPIA Channel Configuration of S1C17M20/M21/M22/M23/M24/M25
Item
Number of channels
Internal clock input
16-bit timer
CLK_T16_m
Clock
generator
Timer
Underflow
Interrupt
controller
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
S1C17M20/M23
24-pin package 32-pin package
SPIA Ch.n
NOCLKDIV
CLK_SPIAn
1/2
Clock/shift register
control circuit
MODEN
SFTRST
LSBFST
CPHA
CPOL
Pull-up/down control
PUEN
Interrupt
TENDIE
control circuit
RBFIE
TBEIE
Figure 13.1.1 SPIA Configuration
Seiko Epson Corporation
13 SYNCHRONOUS SERIAL INTERFACE (SPIA)
S1C17M21/M24
2 channels (Ch.0 and Ch.1)
Ch.0 ← 16-bit timer Ch.1
Ch.1 ← 16-bit timer Ch.2
Shift register
Transmit data buffer
TXD[15:0]
Receive data buffer
RXD[15:0]
circuit
(Used only in slave mode)
TENDIF
RBFIF
TBEIF
S1C17M22/M25
V
DD
SDIn
SDOn
V
DD
SPICLKn
V
DD
V
SS
#SPISSn
13-1