Interrupts; Control Registers; Pwg V D1 Regulator Control Register - Epson S1C17M20 Technical Manual

2 POWER SUPPLY, RESET, AND CLOCKS
Canceling HALT or SLEEP mode
The conditions listed below generate the HALT/SLEEP cancelation signal to cancel HALT or SLEEP mode and
put the CPU into RUN mode. This transition is executed even if the CPU does not accept the interrupt request.
• Interrupt request from a peripheral circuit
• NMI from the watchdog timer
• Debug interrupt
• Reset request

2.5 Interrupts

CLG has a function to generate the interrupts shown in Table 2.5.1.
Interrupt
IOSC oscillation stabiliza-
tion waiting completion
OSC1 oscillation stabili-
zation waiting completion
OSC3 oscillation stabili-
zation waiting completion
OSC1 oscillation stop
OSC3 oscillation auto-
trimming completion
CLG provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the interrupt
controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set. For
more information on interrupt control, refer to the "Interrupt Controller" chapter.

2.6 Control Registers

Note: Do not alter the initial values of the control bits for the functions that are not supported in the
model to be used.
PWG V Regulator Control Register
D1
Register name Bit
PWGVD1CTL 15–8 –
7–2 –
1–0 REGMODE[1:0]
Bits 15–2 Reserved
Bits 1–0 REGMODE[1:0]
These bits control the internal regulator operating mode.
PWGVD1CTL.REGMODE[1:0] bits
2-14
Table 2.5.1 CLG Interrupt Functions
Interrupt flag
CLGINTF.IOSCSTAIF When the IOSC oscillation stabilization waiting
operation has completed after the oscillation starts
CLGINTF.OSC1STAIF When the OSC1 oscillation stabilization waiting
operation has completed after the oscillation starts
CLGINTF.OSC3STAIF When the OSC3 oscillation stabilization waiting
operation has completed after the oscillation starts
CLGINTF.OSC1STPIF When OSC1CLK is stopped, or when the CLGOSC.
OSC1EN or CLGOSC1.OSDEN bit setting is al-
tered from 1 to 0.
CLGINTF.OSC3TEDIF When the OSC3 oscillation auto-trimming opera-
tion has completed
Bit name Initial
0x00
0x00
0x0
Table 2.6.1 Internal Regulator Operating Mode
0x3
0x2
0x1
0x0
Seiko Epson Corporation
Set condition
Reset R/W
– R –
– R
H0 R/WP
Operating mode
Economy mode
Normal mode
Reserved
Automatic mode
S1C17M20/M21/M22/M23/M24/M25
Clear condition
Writing 1
Writing 1
Writing 1
Writing 1
Writing 1
Remarks
TECHNICAL MANUAL (Rev. 1.0)