Clg Interrupt Enable Register; Clg Fout Control Register - Epson S1C17M12 Technical Manual

Each bit corresponds to the interrupt as follows:
CLGINTF.OSC3STAIF bit: OSC3 oscillation stabilization waiting completion interrupt
CLGINTF.IOSCSTAIF bit: IOSC oscillation stabilization waiting completion interrupt
Note: The CLGINTF.IOSCSTAIF bit is 0 after system reset is canceled, but IOSCCLK has already
been stabilized.

CLG Interrupt Enable Register

Register name Bit
CLGINTE 15–8 –
7–3 –
2
1
0
Bits 15–3, 1 Reserved
Bit 2 OSC3STAIE
Bit 0 IOSCSTAIE
These bits enable the CLG interrupts.
1 (R/W): Enable interrupts
0 (R/W): Disable interrupts
Each bit corresponds to the interrupt as follows:
CLGINTE.OSC3STAIE bit: OSC3 oscillation stabilization waiting completion interrupt
CLGINTE.IOSCSTAIE bit: IOSC oscillation stabilization waiting completion interrupt

CLG FOUT Control Register

Register name Bit
CLGFOUT 15–8 –
7
6–4 FOUTDIV[2:0]
3–2 FOUTSRC[1:0]
1
0
Bits 15–7 Reserved
Bits 6–4 FOUTDIV[2:0]
These bits set the FOUT clock division ratio.
Bits 3–2 FOUTSRC[1:0]
These bits select the FOUT clock source.
CLGFOUT.
FOUTDIV[2:0] bits
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Note: When the CLGFOUT.FOUTSRC[1:0] bits are set to 0x3, the FOUT output will be stopped in
SLEEP/HALT mode as SYSCLK is stopped.
Bit 1 Reserved
S1C17M12/M13 TECHNICAL MANUAL
(Rev. 1.2)
Bit name Initial
0x00
0x00
OSC3STAIE 0
– 0
IOSCSTAIE 0
Bit name Initial
0x00
– 0
0x0
0x0
– 0
FOUTEN 0
Table 2.6.8 FOUT Clock Source and Division Ratio Settings
0x0
IOSCCLK
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
Reset R/W
– R –
– R
H0 R/W
– R
H0 R/W
Reset R/W
– R –
– R
H0 R/W
H0 R/W
– R
H0 R/W
CLGFOUT.FOUTSRC[1:0] bits
0x1 0x2
Reserved OSC3CLK
– 1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
Remarks
Remarks
0x3
SYSCLK
Reserved
1/1
2-15