Operations; Initialization - Epson S1C17M20 Technical Manual

14 I 2 C (I2C)
Baud rate generator clock output and operations for supporting clock stretching
Figure 14.3.3.1 shows the clock generated by the baud rate generator and the clock waveform on the I
SCLO (internal signal)
SCLn (external pin)
SCL rising/falling period
Clock stretching period by another I
Baud rate generator counting suspended period
Baud rate generator counting period
Figure 14.3.3.1 Baud Rate Generator Output Clock and SCLn Output Waveform
The baud rate generator output clock SCLO is compared with the SCLn pin status and the results are returned
to the baud rate generator. If a mismatch has occurred between SCLO and SCLn pin levels, the baud rate gen-
erator suspends counting. This extends the clock to control data transfer during the SCL signal rising/falling
period and clock stretching period in which SCL is fixed at low by a slave device.

14.4 Operations

14.4.1 Initialization

The I2C Ch.n should be initialized with the procedure shown below.
When using the I2C in master mode
1. Configure the operating clock and the baud rate generator using the I2CnCLK and I2CnBR registers.
2. Assign the I2C Ch.n input/output function to the ports. (Refer to the "I/O Ports" chapter.)
3. Set the following bits when using the interrupt:
- Write 1 to the interrupt flags in the I2CnINTF register.
- Set the interrupt enable bits in the I2CnINTE register to 1. (Enable interrupts)
4. Set the following I2CnCTL register bits:
- Set the I2CnCTL.MST bit to 1.
- Set the I2CnCTL.SFTRST bit to 1. (Execute software reset)
- Set the I2CnCTL.MODEN bit to 1. (Enable I2C Ch.n operations)
When using the I2C in slave mode
1. Set the following I2CnMOD register bits:
- I2CnMOD.OADR10 bit (Set 10/7-bit address mode)
- I2CnMOD.GCEN bit
2. Set its own address to the I2CnOADR.OADR[9:0] (or OADR[6:0]) bits.
3. Assign the I2C Ch.n input/output function to the ports. (Refer to the "I/O Ports" chapter.)
4. Set the following bits when using the interrupt:
- Write 1 to the interrupt flags in the I2CnINTF register.
- Set the interrupt enable bits in the I2CnINTE register to 1. (Enable interrupts)
5. Set the following I2CnCTL register bits:
- Set the I2CnCTL.MST bit to 0.
- Set the I2CnCTL.SFTRST bit to 1. (Execute software reset)
- Set the I2CnCTL.MODEN bit to 1. (Enable I2C Ch.n operations)
14-4
2 C device
Period in which the internal and external statuses are not matched
(Set master mode)
(Enable response to general call address)
(Set slave mode)
Seiko Epson Corporation
(Clear interrupt flags)
(Clear interrupt flags)
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
2 C bus.