Svd3 Status And Interrupt Flag Register - Epson S1C17M20 Technical Manual

Bits 7–4 SVDRE[3:0]
These bits enable/disable the reset issuance function when a low power supply voltage is detected.
0xa (R/WP):
Other than 0xa (R/WP): Disable (Generate interrupt)
For more information on the SVD3 reset issuance function, refer to "SVD3 Reset."
Bit 3 EXSEL
This bit selects the external voltage to be detected when the SVDCTL.VDSEL bit = 1.
1 (R/WP): EXSVD1
0 (R/WP): EXSVD0
Note: The EXSVD1 pin does not exist depending on the model (see "Power supply voltage to be
detected" in Table 10.1.1). In this case, the external voltage detection function does not work
if the SVDCTL.EXSEL bit is set to 1. When using the external voltage detection function
(SVDCTL.VDSEL bit = 1), the SVDCTL.EXSEL bit should be set to 0.
Bits 2–1 SVDMD[1:0]
These bits select intermittent operation mode and its detection cycle.
Table 10.6.4 Intermittent Operation Mode Detection Cycle Selection
SVDCTL.SVDMD[1:0] bits
For more information on intermittent and continuous operation modes, refer to "SVD3 Operations."
Bit 0 MODEN
This bit enables/disables for the SVD3 circuit to operate.
1 (R/WP): Enable (Start detection operations)
0 (R/WP): Disable (Stop detection operations)
After this bit has been altered, wait until the value written is read out from this bit without subsequent
operations being performed.
Notes: • Writing 0 to the SVDCTL.MODEN bit resets the SVD3 hardware. However, the register values
set and the interrupt flag are not cleared. The SVDCTL.MODEN bit is actually set to 0 after
this processing has finished. If 1 is written to the SVDCTL.MODEN bit continuously without
waiting for the bit being read as 0 at this time, writing 0 may be ignored and a malfunction
may occur as the hardware restarts without resetting.
• The SVD3 internal circuit is initialized if the SVDCTL.SVDSC[1:0] bits, SVDCTL.SVDRE[3:0]
bits, or SVDCTL.SVDMD[1:0] bits are altered while SVD3 is in operation after 1 is written to
the SVDCTL.MODEN bit.

SVD3 Status and Interrupt Flag Register

Register name Bit
SVDINTF 15–9 –
8
7–1 –
0
Bits 15–9 Reserved
Bit 8 SVDDT
The power supply voltage detection results can be read out from this bit.
1 (R): Power supply voltage (V
0 (R): Power supply voltage (V
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
Enable (Issue reset)
0x3 Intermittent operation mode (CLK_SVD3/512)
0x2 Intermittent operation mode (CLK_SVD3/256)
0x1 Intermittent operation mode (CLK_SVD3/128)
0x0
Bit name Initial
0x00
SVDDT x
0x00
SVDIF 0
or EXSVD0/1) < SVD detection voltage V
DD
or EXSVD0/1) ≥ SVD detection voltage V
DD
Seiko Epson Corporation
10 SUPPLY VOLTAGE DETECTOR (SVD3)
Operation mode (detection cycle)
Continuous operation mode
Reset R/W
– R –
– R
– R
H1 R/W Cleared by writing 1.
or EXSVD detection voltage V
or EXSVD detection voltage V
Remarks
SVD
SVD_EXT
SVD
SVD_EXT
10-7