Adc12A Ch.n Configuration Register - Epson S1C17M20 Technical Manual

19 12-BIT A/D CONVERTER (ADC12A)
Bit 7 STMD
This bit selects the data alignment when the conversion results are loaded into the A/D conversion re-
sult registers (ADC12_nADmD.ADmD[15:0] bits).
1 (R/W): Left justify
0 (R/W): Right justify
All the A/D conversion result registers change their data alignment immediately after this bit is al-
tered. This does not affect the conversion results.
Left justified (ADC12_nTRG.STMD bit = 1)
Right justified (ADC12_nTRG.STMD bit = 0) 0
Bit 6 CNVMD
This bit sets the A/D conversion mode.
1 (R/W): Continuous conversion mode
0 (R/W): One-time conversion mode
Bits 5–4 CNVTRG[1:0]
These bits select a trigger source to start A/D conversion.
ADC12_nTRG.CNVTRG[1:0] bits
Bit 3 Reserved
Bits 2–0 SMPCLK[2:0]
These bits set the analog input signal sampling time.
ADC12_nTRG.SMPCLK[2:0] bits

ADC12A Ch.n Configuration Register

Register name Bit
ADC12_nCFG 15–8 –
7–2 –
1–0 VRANGE[1:0]
Note: Make sure that the ADC12_nCTL.BSYSTAT bit is set to 0 before altering the ADC12_nCFG register.
Bits 15–2 Reserved
Bits 1–0 VRANGE[1:0]
These bits set the A/D converter operating voltage range.
19-8
15 14 13
(MSB)
0 0
Figure 19.6.1 Conversion Data Alignment
Table 19.6.2 Trigger Source Selection
0x3
0x2
0x1
0x0 ADC12_nCTL.ADST bit (software trigger)
Table 19.6.3 Sampling Time Settings
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
Bit name Initial
0x00
0x00
0x0
Seiko Epson Corporation
ADC12_nADmD.ADmD[15:0] bits
12 11 10 9 8 7
12-bit conversion result
0 (MSB) 12-bit conversion result
Trigger source
#ADTRGn pin (external trigger)
Reserved
16-bit timer Ch.k underflow
Sampling time
(Number of CLK_T16_k cycles)
11 cycles
10 cycles
9 cycles
8 cycles
7 cycles
6 cycles
5 cycles
4 cycles
Reset R/W
– R –
– R
H0 R/W
S1C17M20/M21/M22/M23/M24/M25
6 5 4 3 2 1 0
(LSB) 0 0 0 0
(LSB)
Remarks
TECHNICAL MANUAL (Rev. 1.0)