Interrupt Processing By The Cpu; Control Registers; Misc Vector Table Address Low Register; Misc Vector Table Address High Register - Epson S1C17M20 Technical Manual

5.7 Interrupt Processing by the CPU

The CPU samples interrupt requests for each cycle. On accepting an interrupt request, the CPU switches to inter-
rupt processing immediately after execution of the current instruction has been completed.
Interrupt processing involves the following steps:
1. The PSR and current program counter (PC) values are saved to the stack.
2. The PSR IE bit is cleared to 0 (disabling subsequent maskable interrupts).
3. The PSR IL[2:0] bits are set to the received interrupt level. (The NMI does not affect the IL bits.)
4. The vector for the interrupt occurred is loaded to the PC to execute the interrupt handler routine.
When an interrupt is accepted, Step 2 prevents subsequent maskable interrupts. Setting the IE bit to 1 in the inter-
rupt handler routine allows handling of multiple interrupts. In this case, since the IL[2:0] bits are changed by Step 3,
only an interrupt with a higher level than that of the currently processed interrupt will be accepted.
Ending interrupt handler routines using the reti instruction returns the PSR to the state before the interrupt occurred.
The program resumes processing following the instruction being executed at the time the interrupt occurred.
Note: When HALT or SLEEP mode is canceled, the CPU jumps to the interrupt handler routine after
executing one instruction. To execute the interrupt handler routine immediately after HALT or
SLEEP mode is canceled, place the nop instruction at just behind the halt/slp instruction.

5.8 Control Registers

MISC Vector Table Address Low Register

Register name Bit
MSCTTBRL 15–8 TTBR[15:8]
7–0 TTBR[7:0]
Bits 15–0 TTBR[15:0]
These bits set the vector table base address (16 low-order bits).

MISC Vector Table Address High Register

Register name Bit
MSCTTBRH 15–8 –
7–0 TTBR[23:16]
Bits 15–8 Reserved
Bits 7–0 TTBR[23:16]
These bits set the vector table base address (eight high-order bits).

ITC Interrupt Level Setup Register x

Register name Bit
ITCLVx 15–11 –
10–8 ILVy
7–3 –
2–0 ILVy
Bits 15–11 Reserved
Bits 7–3 Reserved
Bits 10–8 ILVy [2:0]
1
Bits 2–0 ILVy [2:0]
0
These bits set the interrupt level of each interrupt.
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
Bit name Initial
0x80
0x00
Bit name Initial
0x00
0x00
Bit name Initial
0x00
[2:0] 0x0
1
0x00
[2:0] 0x0
0
(y = 2x +1)
1
(y = 2x)
0
Seiko Epson Corporation
5 INTERRUPT CONTROLLER (ITC)
Reset R/W
H0 R/WP –
H0 R
Reset R/W
– R –
H0 R/WP
Reset R/W
– R –
H0 R/W
– R
H0 R/W
Remarks
Remarks
Remarks
5-5