Control Register; Misc Psr Register; Debug Ram Base Register - Epson S1C17M20 Technical Manual

3 CPU AND DEBUGGER
The following shows the status of the IC with protected Flash:
• The Flash memory data is undefined if it is read from the debugger.
• An error occurs if an attempt is made to program the Flash memory through ICDmini.
However, the Flash security function can be disabled by entering the unprotecting password predefined to GNU17
IDE (the security function will take effect again after a reset). For setting the password, refer to the "(S1C17 Family
C Compiler Package) S5U1C17001C Manual."
Note: Disable the Flash security function before debugging an IC with protected Flash via ICDmini. The
debugging functions may not run normally if the Flash security function is enabled.

3.4 Control Register

MISC PSR Register

Register name Bit
MSCPSR 15–8 –
7–5 PSRIL[2:0]
4
3
2
1
0
Bits 15–8 Reserved
Bits 7–5 PSRIL[2:0]
The value (0 to 7) of the PSR IL[2:0] (interrupt level) bits can be read out with these bits.
Bit 4 PSRIE
The value (0 or 1) of the PSR IE (interrupt enable) bit can be read out with this bit.
Bit 3 PSRC
The value (0 or 1) of the PSR C (carry) flag can be read out with this bit.
Bit 2 PSRV
The value (0 or 1) of the PSR V (overflow) flag can be read out with this bit.
Bit 1 PSRZ
The value (0 or 1) of the PSR Z (zero) flag can be read out with this bit.
Bit 0 PSRN
The value (0 or 1) of the PSR N (negative) flag can be read out with this bit.

Debug RAM Base Register

Register name Bit
DBRAM 31–24 –
23–0 DBRAM[23:0]
Bits 31–24 Reserved
Bits 23–0 DBRAM[23:0]
The start address of the debugging work area (64 bytes) can be read out with these bits.
3-4
Bit name Initial
0x00
0x0
PSRIE 0
PSRC 0
PSRV 0
PSRZ 0
PSRN 0
Bit name Initial
0x00
*1
Seiko Epson Corporation
Reset R/W
– R –
H0 R
H0 R
H0 R
H0 R
H0 R
H0 R
Reset R/W
– R –
H0 R
*1 Debugging work area start address
S1C17M20/M21/M22/M23/M24/M25
Remarks
Remarks
TECHNICAL MANUAL (Rev. 1.0)