Data Transmission In Master Mode - Epson S1C17M20 Technical Manual

14.4.2 Data Transmission in Master Mode

A data sending procedure in master mode and the I2C Ch.n operations are shown below. Figures 14.4.2.1 and 14.4.2.2
show an operation example and a flowchart, respectively.
Data sending procedure
1. Issue a START condition by setting the I2CnCTL.TXSTART bit to 1.
2. Wait for a transmit buffer empty interrupt (I2CnINTF.TBEIF bit = 1) or a START condition interrupt (I2C-
nINTF.STARTIF bit = 1).
Clear the I2CnINTF.STARTIF bit by writing 1 after the interrupt has occurred.
3. Write the 7-bit slave address to the I2CnTXD.TXD[7:1] bits and 0 that represents WRITE as the data trans-
fer direction to the I2CnTXD.TXD0 bit.
4. Wait for a transmit buffer empty interrupt (I2CnINTF.TBEIF bit = 1) generated when an ACK is received or
a NACK reception interrupt (I2CnINTF.NACKIF bit = 1) generated when a NACK is received.
i. Go to Step 5 if transmit data remains when a transmit buffer empty interrupt has occurred.
ii. Go to Step 7 or 1 after clearing the I2CnINTF.NACKIF bit when a NACK reception interrupt has oc-
curred.
5. Write transmit data to the I2CnTXD register.
6. Repeat Steps 4 and 5 until the end of transmit data.
7. Issue a STOP condition by setting the I2CnCTL.TXSTOP bit to 1.
8. Wait for a STOP condition interrupt (I2CnINTF.STOPIF bit = 1).
Clear the I2CnINTF.STOPIF bit by writing 1 after the interrupt has occurred.
Data sending operations
Generating a START condition
The I2C Ch.n starts generating a START condition when the I2CnCTL.TXSTART bit is set to 1. When the
generating operation has completed, the I2C Ch.n clears the I2CnCTL.TXSTART bit to 0 and sets both the
I2CnINTF.STARTIF and I2CnINTF.TBEIF bits to 1.
Sending slave address and data
If the I2CnINTF.TBEIF bit = 1, a slave address or data can be written to the I2CnTXD register. The I2C
Ch.n pulls down SCL to low and enters standby state until data is written to the I2CnTXD register. The
writing operation triggers the I2C Ch.n to send the data to the shift register automatically and to output
eight clock pulses and data bits to the I
When the slave device returns an ACK as the response, the I2CnINTF.TBEIF bit is set to 1. After this inter-
rupt occurs, the subsequent data may be sent or a STOP/repeated START condition may be issued to termi-
nate transmission. If the slave device returns NACK, the I2CnINTF.NACKIF bit is set to 1 without setting
the I2CnINTF.TBEIF bit.
Generating a STOP/repeated START condition
After the I2CnINTF.TBEIF bit is set to 1 (transmit buffer empty) or the I2CnINTF.NACKIF bit is set to 1
(NACK received), setting the I2CnCTL.TXSTOP bit to 1 generates a STOP condition. When the bus free
time (t defined in the I
BUF
I2CnCTL.TXSTOP bit is cleared to 0 and the I2CnINTF.STOPIF bit is set to 1.
When setting the I2CnCTL.TXSTART bit to 1 while the I2CnINTF.TBEIF bit = 1 (transmit buffer empty)
or the I2CnINTF.NACKIF bit = 1 (NACK received), the I2C Ch.n generates a repeated START condition.
When the repeated START condition has been generated, the I2CnINTF.STARTIF and I2CnINTF.TBEIF
bits are both set to 1 same as when a START condition has been generated.
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
C bus.
2
C Specifications) has elapsed after the STOP condition has been generated, the
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14 I 2 C (I2C)
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