Sun Microsystems Ultra 60 Service Manual page 225

The PHY chip integrates a 100BASE-T physical coding sub-layer (PCS) and a
complete 10BASE-T module in a single chip. It provides a standard MII to
communicate between the physical signaling and the medium access control layers
for both 100BASE-X and 10BASE-T operations. The PHY IC interfaces to the 100-
Mbps physical-medium-dependent transceiver Twister IC.
The 100BASE-X portion of the PHY IC consists of the following functional blocks:
The 10BASE-T section of the PHY IC consists of the 10-Mbps transceiver module
with filters.
The 100BASE-T transceiver is included in a separate Twister IC and features
adaptive equalization, baseline wander correction, and transition time control on the
output signals.
The 100BASE-X and 10BASE-T sections share the following functional
characteristics:
The following sections provide brief descriptions of the following:
C.1.12.1 Automatic Negotiation
Automatic negotiation controls the cable when a connection is established to a
network device. It detects the various modes that exist in the linked partner and
advertises its own abilities to automatically configure the highest performance mode
of inter-operation, namely, 10BASE-T, 100BASE-TX, or 100BASE-T4 in half- and full-
duplex modes.
The Ethernet port supports automatic negotiation. At power up, an on-board
transceiver advertises 100BASE-TX in half-duplex mode, which is configured by the
automatic negotiation to the highest common denominator based on the linked
partner.
Transmitter
Receiver
Clock generation module
Clock recovery module
PCS control
MII registers
IEEE 1149.1 controller (JTAG compliance)
IEEE 802.3u auto negotiation
Automatic negotiation
External transceivers
External cables
Connectors
MII power
MII port timing
Appendix C Functional Description C-25