System Controller; C.1.2 System Controller - Sun Microsystems Ultra 60 Service Manual

UPA_ADDRBUS0
<35:0>
Marvin
ASIC
UPA_ADDRBUS1
<28:0>
FIGURE C-2
C.1.2

System Controller

The system controller ASIC, also known as Marvin, implements the central resource
for the UPA protocol. It performs the following functions:
Accepts UPA request packets from the three masters; two processors and
PSYCHO+, and routes them to the correct slave destination.
Maintains cache coherence between the merger buffer in PSYCHO+ and the
processor cache.
Implements blocking rules that guarantee that all requests are properly ordered.
Controls the K9+ ASIC, and so controls the flow of data through the system.
Contains a memory controller that supplies address and control lines to memory.
Receives and distributes resets to all of the UPA clients in the system.
Contains logic for waking up the processor in EnergyStar mode.
UPA_AD0
module
UPA_AD1
module
UPA_AD2
PSYCHO+
UPA_AD3
graphics 0
UPA_AD3
UPA
graphics 1
UPA Address and Data Buses Functional Block Diagram
CPU
UPA_DATA0
0
UPA_DATA1
CPU
1
UPA_DATA3
ASIC
UPA_DATA2
UPA
UPA_DATA2
Appendix C Functional Description
P Bus
XB9+
ASIC
I Bus
C-5