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Texas Instruments TMS320C6743 DSP Technical Reference Manual

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TMS320C6743 DSP

Technical Reference Manual

Literature Number: SPRUH90B

March 2013

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Page 1 TMS320C6743 DSP Technical Reference Manual Literature Number: SPRUH90B March 2013...
Page 2: Table Of Contents
.................... 5.2.8 Reset Considerations ....................5.2.9 Interrupt Support ..................5.2.10 Emulation Considerations ......................MPU Registers ..............5.3.1 Revision Identification Register (REVID) ................5.3.2 Configuration Register (CONFIG) Contents SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 3 7.4.21 Emulation Performance Counter 0 Register (EMUCNT0) ..........7.4.22 Emulation Performance Counter 1 Register (EMUCNT1) ..................Power and Sleep Controller (PSC) ....................... Introduction ................. Power Domain and Module Topology SPRUH90B – March 2013 Contents Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 4 10.2.1 Requirements to Access SYSCFG Registers ....................10.3 Master Priority Control ......................10.4 Interrupt Support ................10.4.1 Interrupt Events and Requests ..................10.4.2 Interrupt Multiplexing ................ 10.4.3 Host-DSP Communication Interrupts Contents SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 5 13.4.12 ECAP Interrupt Forcing Register (ECFRC) ................13.4.13 Revision ID Register (REVID) ..........Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) ....................... 14.1 Introduction ..................... 14.1.1 Introduction ..................14.1.2 Submodule Overview SPRUH90B – March 2013 Contents Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 6 15.3.7 eQEP Position Counter Latch Register (QPOSLAT) ................ 15.3.8 eQEP Unit Timer Register (QUTMR) ............... 15.3.9 eQEP Unit Period Register (QUPRD) ............15.3.10 eQEP Watchdog Timer Register (QWDTMR) Contents SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 7 16.4.2 EDMA3 Channel Controller (EDMA3CC) Registers ............16.4.3 EDMA3 Transfer Controller (EDMA3TC) Registers ........................16.5 Tips ....................16.5.1 Debug Checklist ..............16.5.2 Miscellaneous Programming/Debug Tips ....................16.6 Setting Up a Transfer SPRUH90B – March 2013 Contents Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 8 18.2.11 Memory Map ..................18.2.12 Priority and Arbitration ..................18.2.13 System Considerations ..................18.2.14 Power Management ................... 18.2.15 Emulation Considerations ....................18.3 Example Configuration .................... 18.3.1 Hardware Interface Contents SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 9 19.4.4 SDRAM Timing 1 Register (SDTIM1) ............... 19.4.5 SDRAM Timing 2 Register (SDTIM2) .............. 19.4.6 SDRAM Configuration 2 Register (SDCFG2) ............19.4.7 Peripheral Bus Burst Priority Register (BPRIO) SPRUH90B – March 2013 Contents Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 10 21.1.3 Functional Block Diagram ............... 21.1.4 Industry Standard(s) Compliance Statement ....................... 21.2 Architecture ....................21.2.1 Bus Structure ....................21.2.2 Clock Generation ..................21.2.3 Clock Synchronization .................... 21.2.4 Signal Descriptions Contents SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 11 22.2.6 EDMA Event Support ................... 22.2.7 Power Management ........................22.3 Registers ..................22.3.1 Register Bit Restrictions ..............22.3.2 Revision Identification Register (REV) ................22.3.3 Pin Function Register (PFUNC) SPRUH90B – March 2013 Contents Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 12 23.1.1 Purpose of the Peripheral ......................23.1.2 Features ..................23.1.3 Functional Block Diagram ................23.1.4 Supported Use Case Statement ............... 23.1.5 Industry Standard(s) Compliance Statement ....................... 23.2 Architecture Contents SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 13 Introduction 1036 ................... 24.1.1 Purpose of the Peripheral 1036 ....................... 24.1.2 Features 1036 ................... 24.1.3 Functional Block Diagram 1037 ............. 24.1.4 Industry Standard(s) Compliance Statement 1037 SPRUH90B – March 2013 Contents Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 14 25.2.1 Architecture – General-Purpose Timer Mode 1092 ..............25.2.2 Architecture – Watchdog Timer Mode 1104 ..................25.2.3 Reset Considerations 1106 ....................25.2.4 Interrupt Support 1106 ..................25.2.5 DMA Event Support 1106 Contents SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 15 26.3.9 Modem Status Register (MSR) 1150 ................26.3.10 Scratch Pad Register (SCR) 1151 ................26.3.11 Divisor Latches (DLL and DLH) 1151 ..........26.3.12 Revision Identification Registers (REVID1 and REVID2) 1153 SPRUH90B – March 2013 Contents Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 16 ........26.3.13 Power and Emulation Management Register (PWREMU_MGMT) 1154 ................26.3.14 Mode Definition Register (MDR) 1155 ......................Revision History 1156 Contents SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 17 7-20. Clock Status Register (CKSTAT) .................. 7-21. SYSCLK Status Register (SYSTAT) ............7-22. Emulation Performance Counter 0 Register (EMUCNT0) ............7-23. Emulation Performance Counter 1 Register (EMUCNT1) SPRUH90B – March 2013 List of Figures Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 18 ..............10-28. Pin Multiplexing Control 10 Register (PINMUX10) ..............10-29. Pin Multiplexing Control 11 Register (PINMUX11) ..............10-30. Pin Multiplexing Control 12 Register (PINMUX12) List of Figures SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 19 14-3. ePWM Submodules and Critical Internal Signal Interconnects ................14-4. Time-Base Submodule Block Diagram ............... 14-5. Time-Base Submodule Signals and Registers ..................14-6. Time-Base Frequency and Period SPRUH90B – March 2013 List of Figures Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 20 14-47. Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz ....... 14-48. High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz ....................14-49. Simplified ePWM Module List of Figures SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 21 15-1. Optical Encoder Disk ............. 15-2. QEP Encoder Output Signal for Forward/Reverse Movement ....................15-3. Index Pulse Example ..............15-4. Functional Block Diagram of the eQEP Peripheral SPRUH90B – March 2013 List of Figures Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 22 16-5. A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) ..........16-6. AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) ....................... 16-7. PaRAM Set ....................16-8. Linked Transfer Example List of Figures SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 23 16-55. DMA Region Access Enable Register for Region m (DRAEm) ............16-56. QDMA Region Access Enable for Region m (QRAEm) ................. 16-57. Event Queue Entry Registers (QxEy) SPRUH90B – March 2013 List of Figures Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 24 16-104. Destination FIFO Source Address Register n (DFSRCn) ..............16-105. Destination FIFO Count Register n (DFCNTn) ............ 16-106. Destination FIFO Destination Address Register n (DFDSTn) List of Figures SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 25 17-42. Receive Revision ID Register (RXREVID) ................17-43. Receive Control Register (RXCONTROL) ..............17-44. Receive Teardown Register (RXTEARDOWN) ..........17-45. Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) SPRUH90B – March 2013 List of Figures Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 26 18-4. EMIFA to 512K × 16 × 2 bank SDRAM Interface .............. 18-5. Timing Waveform for Basic SDRAM Read Operation ............... 18-6. Timing Waveform for Basic SDRAM Write Operation List of Figures SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 27 18-53. NAND Flash 4-Bit ECC Error Value Register 2 (NANDERRVAL2) ..................19-1. EMIFB Functional Block Diagram ............... 19-2. Timing Waveform of SDRAM PRE Command SPRUH90B – March 2013 List of Figures Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 28 20-21. GPIO Banks 4 and 5 Clear Data Register (CLR_DATA45) ............20-22. GPIO Banks 6 and 7 Clear Data Register (CLR_DATA67) ..............20-23. GPIO Bank 8 Clear Data Register (CLR_DATA8) List of Figures SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 29 21-15. I2C Interrupt Status Register (ICSTR) ..............21-16. I2C Clock Low-Time Divider Register (ICCLKL) ..............21-17. I2C Clock High-Time Divider Register (ICCLKH) ..................21-18. I2C Data Count Register (ICCNT) SPRUH90B – March 2013 List of Figures Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 30 ................22-30. Data Flow Through Receive Format Unit ................. 22-31. Audio Mute (AMUTE) Block Diagram ............22-32. Transmit Clock Failure Detection Circuit Block Diagram List of Figures SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 31 22-78. Write FIFO Control Register (WFIFOCTL) ................22-79. Write FIFO Status Register (WFIFOSTS) ................22-80. Read FIFO Control Register (RFIFOCTL) ................22-81. Read FIFO Status Register (RFIFOSTS) SPRUH90B – March 2013 List of Figures Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 32 24-5. SPI 5-Pin Option with SPIx_ENA and SPIx_SCS[n] 1049 ................. 24-6. Format for Transmitting 12-Bit Word 1050 ..................24-7. Format for 10-Bit Received Word 1050 List of Figures SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 33 25-14. Emulation Management Register (EMUMGT) 1110 ............. 25-15. GPIO Interrupt Control and Enable Register (GPINTGPEN) 1111 ............... 25-16. GPIO Data and Direction Register (GPDATGPDIR) 1112 SPRUH90B – March 2013 List of Figures Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 34 ................ 26-22. Revision Identification Register 2 (REVID2) 1153 ..........26-23. Power and Emulation Management Register (PWREMU_MGMT) 1154 ..................26-24. Mode Definition Register (MDR) 1155 List of Figures SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 35 List of Tables ......................2-1. DSP Interrupt Map ..............3-1. TMS320C6743 DSP System Interconnect Matrix ....................5-1. MPU Memory Regions ..................... 5-2. MPU2 Default Configuration ....................5-3. Device Master Settings ..................5-4. Request Type Access Controls ................5-5. MPU_BOOTCFG_ERR Interrupt Sources ................
Page 36 10-17. Fault Address Register (FLTADDRR) Field Descriptions ..............10-18. Fault Status Register (FLTSTAT) Field Descriptions ............10-19. Master Priority 0 Register (MSTPRI0) Field Descriptions List of Tables SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 37 13-18. Capture 3 Register (CAP3) Field Descriptions ............... 13-19. Capture 4 Register (CAP4) Field Descriptions ............13-20. ECAP Control Register 1 (ECCTL1) Field Descriptions SPRUH90B – March 2013 List of Tables Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 38 14-39. EPWM2 Initialization for ....................14-40. EPWM1 Initialization for ....................14-41. EPWM2 Initialization for ....................14-42. EPWM1 Initialization for ....................14-43. EPWM2 Initialization for List of Tables SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 39 15-3. eQEP Position Counter Register (QPOSCNT) Field Descriptions ........15-4. eQEP Position Counter Initialization Register (QPOSINIT) Field Descriptions ........15-5. eQEP Maximum Position Count Register (QPOSMAX) Field Descriptions SPRUH90B – March 2013 List of Tables Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 40 16-24. DMA Channel Queue Number Register n (DMAQNUMn) Field Descriptions ..................... 16-25. Bits in DMAQNUMn ........16-26. QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions ..............16-27. Event Missed Register (EMR) Field Descriptions List of Tables SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 41 16-74. Source Active Destination Address Register (SADST) Field Descriptions ............. 16-75. Source Active B-Index Register (SABIDX) Field Descriptions ......16-76. Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions SPRUH90B – March 2013 List of Tables Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 42 17-32. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) Field ....................... Descriptions ..........17-33. MDIO User Access Register 0 (USERACCESS0) Field Descriptions ........17-34. MDIO User PHY Select Register 0 (USERPHYSEL0) Field Descriptions List of Tables SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 43 17-80. MAC Address Low Bytes Register (MACADDRLO) Field Descriptions ........... 17-81. MAC Address High Bytes Register (MACADDRHI) Field Descriptions .............. 17-82. MAC Index Register (MACINDEX) Field Descriptions SPRUH90B – March 2013 List of Tables Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 44 ................18-43. NAND Flash Write Timing Requirements ............18-44. EMIFA Timing Requirements for HY27UA081G1M Example ..........18-45. NAND Flash Timing Requirements for HY27UA081G1M Example List of Tables SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 45 19-18. SDRAM Memory Controller FIFO Description ......................19-19. Reset Sources ....................19-20. SDCFG Configuration ....................19-21. SDRFC Configuration ....................19-22. SDTIM1 Configuration ....................19-23. SDTIM2 Configuration SPRUH90B – March 2013 List of Tables Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 46 21-15. Master-Transmitter/Receiver Bus Activity Defined by RM, STT, and STP Bits ............21-16. How the MST and FDF Bits Affect the Role of TRX Bit ............21-17. I2C Interrupt Vector Register (ICIVR) Field Descriptions List of Tables SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 47 22-36. Transmit Bit Stream Format Register (XFMT) Field Descriptions .......... 22-37. Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions ..........22-38. Transmit Clock Control Register (ACLKXCTL) Field Descriptions SPRUH90B – March 2013 List of Tables Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 48 ............... 24-5. SPI Register Settings Defining Slave Modes 1042 ..............24-6. Allowed SPI Register Settings in Slave Modes 1042 ......................24-7. Clocking Modes 1051 List of Tables SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 49 26-2. Baud Rate Examples for 150-MHZ UART Input Clock and 13× Over-sampling Mode 1127 ..................... 26-3. UART Signal Descriptions 1128 ..................26-4. Character Time for Word Lengths 1131 SPRUH90B – March 2013 List of Tables Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 50 26-24. Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions 1154 ............... 26-25. Mode Definition Register (MDR) Field Descriptions 1155 ................... A-1. Document Revision History 1156 List of Tables SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 51: About This Manual
CPU pipeline stalls. If the data requested by the CPU is not contained in cache, it is fetched from the next lower memory level, L2 or external memory. Code Composer Studio is a trademark of Texas Instruments. SD is a trademark of SanDisk Corporation.
Page 52: Overview
Chapter 1 SPRUH90B – March 2013 Overview ........................... Topic Page ...................... Introduction ....................Block Diagram ....................DSP Subsystem ....................DMA Subsystem Overview SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 53: Introduction
(L1P, L1D, and L2). The DSP Subsystem chapter describes the DSPSS components. DMA Subsystem The DMA subsystem includes two instances of the enhanced DMA controller (EDMA3). For more information, see the Enhanced Direct Memory Access (EDMA3) Controller chapter. Figure 1-1. TMS320C6743 DSP Block Diagram DSP Subsystem JTAG Interface System Control C674x™...
Page 54: Dsp Subsystem
Chapter 2 SPRUH90B – March 2013 DSP Subsystem ........................... Topic Page ...................... Introduction ................TMS320C674x Megamodule ..................... Memory Map ............... Advanced Event Triggering (AET) DSP Subsystem SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 55: Introduction
IDMA file A file B Bandwidth Mgmt Configuration peripherals Memory protect Cache control MDMA SDMA 8x32 32K bytes High performance L1D RAM/ switch fabric cache SPRUH90B – March 2013 DSP Subsystem Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 56: Tms320C674X Megamodule
C674x Interrupt Control 0 EVT1 C674x Interrupt Control 1 EVT2 C674x Interrupt Control 2 EVT3 C674x Interrupt Control 3 T64P0_TINT12 Timer64P0 - TINT12 SYSCFG_CHIPINT2 SYSCFG CHIPSIG Register DSP Subsystem SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 57 EMIFB Memory Error Interrupt MCASP_INT McASP0,1 Combined RX/TX Interrupts GPIO_B6INT GPIO Bank 6 Interrupt — Reserved T64P0_TINT34 Timer64P0 Interrupt 34 GPIO_B0INT GPIO Bank 0 Interrupt SPRUH90B – March 2013 DSP Subsystem Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 58 Reserved UMC_ED1 C674x-UMC UMC_ED2 C674x-UMC PDC_INT C674x-PDC SYS_CMPA C674x-SYS PMC_CMPA C674x-PMC PMC_CMPA C674x-PMC DMC_CMPA C674x-DMC DMC_CMPA C674x-DMC UMC_CMPA C674x-UMC UMC_CMPA C674x-UMC EMC_CMPA C674x-EMC EMC_BUSERR C674x-EMC DSP Subsystem SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 59 Software can initiate static power-down by way of a register bit in the power-down controller command register (PDCCMD) of the PDC. For more information on the PDC, see the TMS320C674x DSP Megamodule Reference Guide (SPRUFK5). SPRUH90B – March 2013 DSP Subsystem Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 60: Memory Map
See the System Interconnect chapter and the System Memory chapter for a description of the additional system memory and peripherals that the DSP has access to. DSP Subsystem SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 61: Advanced Event Triggering (Aet)
Counters: count the occurrence of an event or cycles for performance monitoring. • State Sequencing: allows combinations of hardware program breakpoints and data watchpoints to precisely generate events for complex sequences. SPRUH90B – March 2013 DSP Subsystem Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 62: System Interconnect
Chapter 3 SPRUH90B – March 2013 System Interconnect ........................... Topic Page ...................... Introduction ..............System Interconnect Block Diagram System Interconnect SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 63: Introduction
EDMA3 or on a CPU to perform transfers to and from them. The system master peripherals include the DSP, the EDMA3 transfer controllers, EMAC. Not all master peripherals may connect to all slave peripherals. The supported connections are designated by an X in Table 3-1. Table 3-1. TMS320C6743 DSP System Interconnect Matrix Masters Slaves Default Peripheral...
Page 64: System Interconnect Block Diagram
SCR10 Asynchronous Bridge EDMA3 TC0 eCAP1 EDMA3 TC1 eCAP2 Paths with dashed lines cross the subchip boundary eQEP0 eQEP1 EDMA3 CC EDMA3 CC PRU Cfg System Interconnect SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 65: System Memory
Chapter 4 SPRUH90B – March 2013 System Memory ........................... Topic Page ...................... Introduction ....................DSP Memories ..................... External Memories ................... Internal Peripherals ....................... Peripherals SPRUH90B – March 2013 System Memory Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 66: Introduction
The DSP has access to all peripherals on the device. See the device-specific data manual for the complete list of peripherals supported on your device. System Memory SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 67: Memory Protection Unit (Mpu)
Chapter 5 SPRUH90B – March 2013 Memory Protection Unit (MPU) ........................... Topic Page ...................... Introduction ...................... Architecture ....................MPU Registers SPRUH90B – March 2013 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 68: Introduction
(MPU_ADDR_ERR_INT) and a protection interrupt (MPU_PROT_ERR_INT). Figure 5-1. MPU Block Diagram Input Output Protection Data Data Checks MPU_ADDR_ERR_INT MMRs MPU_PROT_ERR_INT MPU Register Bus Memory Protection Unit (MPU) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 69: Mpu Default Configuration
Privilege ID Privilege Level Access Type EDMA3CC Inherited Inherited EDMA3TC0 and TC1 Inherited Inherited Software dependant Software dependant PRU0/PRU1 Supervisor EMAC Supervisor Data/DMA SPRUH90B – March 2013 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 70: Memory Protection Ranges
When set to 1, the AID bit grants access to the corresponding ID. When cleared to 0, the AID bit denies access to the corresponding requestor. Memory Protection Unit (MPU) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 71: Protection Check
RX, then the final permission is just R. The MPU has a special mechanism for handling DSP L1/L2 cache controller read accesses, see Section 5.2.5 for more details. SPRUH90B – March 2013 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 72: Dsp L1/L2 Cache Controller Accesses
MPU_PROT_ERR_INT interrupt is generated when there is a protection violation of either in the defined ranges or to the MPU registers. The transfer parameters that caused the violation are saved in the MPU registers. Memory Protection Unit (MPU) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 73: Emulation Considerations
01E1 5244h PROG5_MPEAR Programmable range 5 end address register Section 5.3.11 01E1 5248h PROG5_MPPA Programmable range 5 memory protection page attributes register Section 5.3.12 SPRUH90B – March 2013 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 74: Revision Identification Register (Revid)
LEGEND: R = Read only; -n = value after reset Table 5-7. Revision ID Register (REVID) Field Descriptions Field Value Description 31-0 4E81 0101h Revision ID of the MPU. Memory Protection Unit (MPU) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 75: Configuration Register (Config)
Assume allowed. When an address is not covered by any MPU protection range, this bit determines whether the transfer is assumed to be allowed or not allowed. Assume is disallowed. Assume is allowed. SPRUH90B – March 2013 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 76: Interrupt Raw Status/Set Register (Irawstat)
Protection violation error. Reading this bit reflects the status of the interrupt. Writing 1 sets the status; writing 0 has no effect. Interrupt is not set. Interrupt is set. Memory Protection Unit (MPU) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 77: Interrupt Enable Status/Clear Register (Ienstat)
If the interrupt is disabled, reading this bit returns 0. Writing 1 sets the status; writing 0 has no effect. Interrupt is not set. Interrupt is set. SPRUH90B – March 2013 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 78: Interrupt Enable Set Register (Ienset)
Address violation error disable. Writing 0 has no effect. Interrupt is cleared/disabled. PROTERR_CLR Protection violation error disable. Writing 0 has no effect. Interrupt is cleared/disabled. Memory Protection Unit (MPU) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 79: Fixed Range Start Address Register (Fxd_Mpsar)
(FXD_MPSAR), which instead read as 0. The FXD_MPEAR is shown in Figure 5-10. Figure 5-10. Fixed Range End Address Register (FXD_MPEAR) Reserved LEGEND: R = Read only; -n = value after reset SPRUH90B – March 2013 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 80: Fixed Range Memory Protection Page Attributes Register (Fxd_Mppa)
Access is denied. Access is allowed. User Write permission. Access is denied. Access is allowed. User Execute permission. Access is denied. Access is allowed. Memory Protection Unit (MPU) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 81: Programmable Range N Start Address Registers (Progn_Mpsar)
Table 5-14. MPU2 Programmable Range n Start Address Register (PROGn_MPSAR) Field Descriptions Field Value Description 31-16 START_ADDR C000h–DFFFh Start address for range N. 15-0 Reserved Reserved SPRUH90B – March 2013 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 82: Programmable Range N End Address Registers (Progn_Mpear)
Table 5-15. MPU2 Programmable Range n End Address Register (PROGn_MPEAR) Field Descriptions Field Value Description 31-16 END_ADDR C000h–DFFFh Start address for range N. 15-0 Reserved FFFFh Reserved Memory Protection Unit (MPU) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 83: Programmable Range N Memory Protection Page Attributes Register (Progn_Mppa)
Access is denied. Access is allowed. User Write permission. Access is denied. Access is allowed. User Execute permission. Access is denied. Access is allowed. SPRUH90B – March 2013 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 84: Fault Address Register (Fltaddrr)
LEGEND: R = Read only; -n = value after reset Table 5-17. Fault Address Register (FLTADDRR) Field Descriptions Field Value Description 31-0 FLTADDR 0-FFFF FFFFh Memory address of fault. Memory Protection Unit (MPU) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 85: Fault Status Register (Fltstat)
9h-Fh Reserved Supervisor write fault. Reserved Relaxed cache write back fault. 13h-1Fh Reserved Supervisor read fault. 21h-3Eh Reserved Relaxed cache line fill fault. SPRUH90B – March 2013 Memory Protection Unit (MPU) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 86: Fault Clear Register (Fltclr)
Value Description 31-1 Reserved Reserved CLEAR Command to clear the current fault. Writing 0 has no effect. No effect. Clear the current fault. Memory Protection Unit (MPU) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 87: Device Clocking
Chapter 6 SPRUH90B – March 2013 Device Clocking ........................... Topic Page ......................Overview ..................Frequency Flexibility ................... Peripheral Clocking SPRUH90B – March 2013 Device Clocking Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 88: Overview
EMIFA SYSCLK3 SYSCFG, PSCs, I2C1, EMAC/MDIO, GPIO SYSCLK4 EMIFB I/O Clock SYSCLK5 EMAC SYSCLK7 I2C0, Timers, McASP serial clock AUXCLK Not Applicable PLL Bypass Clock Device Clocking SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 89: Frequency Flexibility
PLLDIV blocks that creates each of the system clock domains (SYSCLK1-SYSCLK7). Each SYSCLK has a PLLDIV block associated with it. See the Phase-Locked Loop Controller (PLLC) chapter for more details on the PLL. SPRUH90B – March 2013 Device Clocking Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 90: Example Pll Frequencies
CPU frequency of 200 MHz. Table 6-3. Example PLL Frequencies Multiplier OSCIN Frequency Frequency PLL Multiplier (MHz) Div1 Div2 Div3 Div4 112.5 Device Clocking SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 91: Peripheral Clocking
EMIFB via the LPSC while still providing a clock on the EMB_CLK. NOTE: EMB_CLK is only an output clock. EMIFB does not support an externally provided input clock. SPRUH90B – March 2013 Device Clocking Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 92: Emifb Clocking Diagram
100 MHz Div3 133 MHz 89 MHz 133 MHz Div4 100 MHz 89 MHz 133 MHz Section 6.2 for an explanation of POSTDIV divider modes. Device Clocking SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 93: Emifa Clocking
66.6 MHz 100 MHz Div3 133 MHz 89 MHz 66.5 MHz Div4 100 MHz 89 MHz 100 MHz Section 6.2 for explanation of POSTDIV divider modes. SPRUH90B – March 2013 Device Clocking Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 94: Emac Clocking
0010 0000 3-State 0000 0010 RMII_MHZ_50_CLK Signal NOTE: The SYSCLK7 output clock does not meet the RMII reference clock specification of 50 MHz +/-50 ppm. Device Clocking SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 95: Emac Reference Clock Frequencies
Div4 112.5 MHz Not Applicable Section 6.2 for explanation of POSTDIV divider modes. Certain PLL configurations do not support a 50 MHz clock on SYSCLK7. SPRUH90B – March 2013 Device Clocking Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 96: I/O Domains
SPI0 SYSCLK2 or clocks, or externally generated Peripheral Serial Clock asynchronous clocks. I2C1 SYSCLK4 or Peripheral Serial Clock EMAC SYSCLK7 or RMII_MHZ_50_CLK Device Clocking SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 97: Phase-Locked Loop Controller (Pllc)
SPRUH90B – March 2013 Phase-Locked Loop Controller (PLLC) ........................... Topic Page ...................... Introduction ....................PLL0 Control ............Locking/Unlocking PLL Register Access ....................PLLC Registers SPRUH90B – March 2013 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 98: Introduction
PLL mode operation (set the PLLEN bit in PLLCTL to 1). Registers used in PLLC0 are listed in Section 7.4. Phase-Locked Loop Controller (PLLC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 99: Pll0 Structure
SYSCLK3 PLLDIV4 (/4) SYSCLK4 PLLDIV5 (/3) SYSCLK5 PLLDIV7 (/6) SYSCLK7 AUXCLK EMIFA Internal Clock DIV4.5 Source CFGCHIP3[EMA_CLKSRC] EMIFB DIV4.5 Internal Clock Source CFGCHIP3[EMB_CLKSRC] SPRUH90B – March 2013 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 100: Device Clock Generation
The DIV4P5 (/4.5) hardware clock divider is provided to generate 133 MHz from the 600 MHz PLL clock for use as clocks to the EMIFs. See Figure 7-1. Phase-Locked Loop Controller (PLLC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 101: Steps For Changing Pll0 Domain Frequency
8. Wait for PLL to lock. See the device-specific data manual for PLL lock time. 9. Set the PLLEN bit in PLLCTL to 1 to remove the PLL from bypass mode. SPRUH90B – March 2013 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 102: Locking/Unlocking Pll Register Access
NOTE: The PLL_MASTER_LOCK bit in CFGCHIP0 defaults to unlocked after reset, so the above procedure is only required after the PLL_MASTER_LOCK bit has been locked (set to 1). Phase-Locked Loop Controller (PLLC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 103: Pllc Registers
PLL Controller Divider 7 Register Section 7.4.12 01C1 11F0h EMUCNT0 Emulation Performance Counter 0 Register Section 7.4.21 01C1 11F4h EMUCNT1 Emulation Performance Counter 1 Register Section 7.4.22 SPRUH90B – March 2013 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 104: Revision Identification Register (Revid)
Power on reset. Power On Reset (POR) was not the last reset to occur. Power On Reset (POR) was the last reset to occur. Phase-Locked Loop Controller (PLLC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 105: Pll Control Register (Pllctl)
PLL reset is not asserted Reserved Reserved PLLPWRDN PLL power-down. PLL operation PLL power-down PLLEN PLL mode enables. Bypass mode PLL mode, not bypassed SPRUH90B – March 2013 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 106: Pll Multiplier Control Register (Pllm)
Disable Enable 14-5 Reserved Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL pre-divide by 1). Phase-Locked Loop Controller (PLLC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 107: Pll Controller Divider 1 Register (Plldiv1)
Disable Enable 14-5 Reserved Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 1 (PLL divide by 2). SPRUH90B – March 2013 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 108: Pll Controller Divider 3 Register (Plldiv3)
Divider Enable. Disable Enable 14-5 Reserved Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults 3 (PLL divide by 4). Phase-Locked Loop Controller (PLLC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 109: Pll Controller Divider 5 Register (Plldiv5)
Disable Enable 14-5 Reserved Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 0 (PLL divide by 1). SPRUH90B – March 2013 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 110: Pll Controller Divider 7 Register (Plldiv7)
Disable Enable 14-5 Reserved Reserved RATIO 0-1Fh Divider ratio. Divider Value = RATIO + 1. RATIO defaults to 5 (PLL divide by 6). Phase-Locked Loop Controller (PLLC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 111: Pll Post-Divider Control Register (Postdiv)
Table 7-16. PLL Controller Command Register (PLLCMD) Field Descriptions Field Value Description 31-1 Reserved Reserved GOSET GO bit for SYSCLKx phase alignment. Clear bit (no effect) Phase alignment SPRUH90B – March 2013 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 112: Pll Controller Status Register (Pllstat)
Status of GO operation. If 1, indicates GO operation is in progress. GO operation is not in progress. GO operation is in progress. Phase-Locked Loop Controller (PLLC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 113: Pll Controller Clock Align Control Register (Alnctl)
SYSCLK2 needs to be aligned to others selected in this register. ALN1 SYSCLK1 needs to be aligned to others selected in this register. SPRUH90B – March 2013 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 114: Plldiv Ratio Change Status Register (Dchange)
SYSCLK2 divide ratio is modified. Ratio is not modified. Ratio is modified. SYS1 SYSCLK1 divide ratio is modified. Ratio is not modified. Ratio is modified. Phase-Locked Loop Controller (PLLC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 115: Clock Enable Control Register (Cken)
Reserved. Write the default value when modifying this register. AUXEN AUXCLK enable. Actual AUXCLK status is shown in the clock status register (CKSTAT). AUXCLK is disabled. AUXCLK is enabled. SPRUH90B – March 2013 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 116: Clock Status Register (Ckstat)
AUXCLK on status. AUXCLK is controlled by the AUXEN bit in the clock enable control register (CKEN). AUXCLK is off. AUXCLK is on. Phase-Locked Loop Controller (PLLC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 117: Sysclk Status Register (Systat)
SYSCLK6 on status SYS5ON SYSCLK5 on status SYS4ON SYSCLK4 on status SYS3ON SYSCLK3 on status SYS2ON SYSCLK2 on status SYS1ON SYSCLK1 on status SPRUH90B – March 2013 Phase-Locked Loop Controller (PLLC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 118: Emulation Performance Counter 0 Register (Emucnt0)
LEGEND: R = Read only; -n = value after reset Table 7-24. Emulation Performance Counter 1 Register (EMUCNT1) Field Descriptions Field Value Description 31-0 COUNT 0-FFFF FFFFh Counter value for upper 64-bits. Phase-Locked Loop Controller (PLLC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 119: Power And Sleep Controller (Psc)
Power Domain and Module Topology ................Executing State Transitions ..............IcePick Emulation Support in the PSC ....................PSC Interrupts ....................PSC Registers SPRUH90B – March 2013 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 120: Introduction
— Not Used — — — UART0 AlwaysON (PD0) SwRstDisable — Not Used — — — SCR1 (BR4) AlwaysON (PD0) Enable 120 Power and Sleep Controller (PSC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 121: Psc1 Default Module Configuration
— SCR8 (BR15) AlwaysON (PD0) Enable Not Used — — — SCR12 (BR18) AlwaysON (PD0) Enable 27-31 Not Used — — — SPRUH90B – March 2013 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 122: Power Domain States
Disable, SyncReset, or SwRstDisable state the power sleep controller ignores these transition requests and transitions the module state to Enable. 122 Power and Sleep Controller (PSC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 123 2. Set the LRST bit in the module control register (MDCTLn) to 1 to de-assert module’s local reset. If the CPU is in the enable state, it immediately executes program instructions after reset is de-asserted. SPRUH90B – March 2013 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 124: Executing State Transitions
4. Wait for the GOSTAT[x] bit in PTSTAT to clear to 0. The modules are safely in the new states only after the GOSTAT[x] bit in PTSTAT is cleared to 0. Power and Sleep Controller (PSC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 125: Icepick Emulation Support In The Psc
NEXT bit in the MDCTL/PDCTL registers. IcePick support only applies to the modules listed in Section 8.4; therefore, the PSC interrupt conditions only apply to those modules listed. SPRUH90B – March 2013 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 126: Interrupt Registers
(MERRCR0), or the bit corresponding to the power domain number in the power error clear register (PERRCR) in PSC0 module. Power and Sleep Controller (PSC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 127: Interrupt Handling
(d) Set the ALLEV bit in INTEVAL. Setting this bit reasserts the PSC interrupt to the device interrupt controller, if there are still any active interrupt events. SPRUH90B – March 2013 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 128: Psc Registers
Module Status n Register (modules 0-31) Section 8.6.17 01E2 787Ch MDSTAT31 01E2 7A00h- MDCTL0- Module Control n Register (modules 0-31) Section 8.6.19 01E2 7A7Ch MDCTL31 128 Power and Sleep Controller (PSC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 129: Revision Identification Register (Revid)
Reserved Reserved ALLEV Evaluate PSC interrupt (PSCn_ALLINT). A write of 0 has no effect. A write of 1 re-evaluates the interrupt condition. SPRUH90B – March 2013 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 130: Psc0 Module Error Pending Register 0 (Modules 0-15) (Merrpr0)
Figure 8-4. Figure 8-4. PSC1 Module Error Pending Register 0 (MERRPR0) Reserved LEGEND: R = Read only; -n = value after reset Power and Sleep Controller (PSC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 131: Psc0 Module Error Clear Register 0 (Modules 0-15) (Merrcr0)
Figure 8-6. Figure 8-6. PSC1 Module Error Clear Register 0 (MERRCR0) Reserved LEGEND: R = Read only; -n = value after reset SPRUH90B – March 2013 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 132: Power Error Pending Register (Perrpr)
A write of 0 has no effect. A write of 1 clears the P bit in PERRPR and the interrupt status bits in PDSTAT1. Reserved Reserved Power and Sleep Controller (PSC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 133: Power Domain Transition Command Register (Ptcmd)
MDCTL.NEXT for all the modules residing on this domain). If any of the NEXT fields are not matching the corresponding current state (MDSTAT.STATE), the PSC will transition those respective domain/modules to the new NEXT state. SPRUH90B – March 2013 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 134: Power Domain Transition Status Register (Ptstat)
Always ON (PD0) power domain transition status. No transition in progress. Modules in Always ON power domain are transitioning. Always On power domain is transitioning. Power and Sleep Controller (PSC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 135: Power Domain 0 Status Register (Pdstat0)
Power domain is in the off state. Power domain is in the on state. 2h-Fh Reserved 10h-1Ah Power domain is in transition. 1Bh-1Fh Reserved SPRUH90B – March 2013 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 136: Power Domain 1 Status Register (Pdstat1)
Power domain is in the off state. Power domain is in the on state. 2h-Fh Reserved 10h-1Ah Power domain is in transition. 1Bh-1Fh Reserved Power and Sleep Controller (PSC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 137: Power Domain 0 Control Register (Pdctl0)
Power domain next state. For Always ON power domain this bit is read/write, but writes have no effect since internally this power domain always remains in the on state. Power domain off. Power domain on. SPRUH90B – March 2013 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 138: Power Domain 1 Control Register (Pdctl1)
Emulation alters power domain state interrupt enable. Disable interrupt. Enable interrupt. Reserved Reserved Reserved Reserved NEXT User-desired power domain next state. Power domain off. Power domain on. Power and Sleep Controller (PSC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 139: Power Domain 0 Configuration Register (Pdcfg0)
Not a RAM power domain. RAM power domain. ALWAYSON Always ON power domain. Not an Always ON power domain. Always ON power domain. SPRUH90B – March 2013 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 140: Power Domain 1 Configuration Register (Pdcfg1)
Not a RAM power domain. RAM power domain. ALWAYSON Always ON power domain. Not an Always ON power domain. Always ON power domain. Power and Sleep Controller (PSC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 141: Module Status N Register (Mdstatn)
Reserved Reserved STATE 0-3Fh Module state status: indicates current module status. SwRstDisable state SyncReset state Disable state Enable state 4h-3Fh Indicates transition SPRUH90B – March 2013 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 142: Psc0 Module Control N Register (Modules 0-15) (Mdctln)
Module local reset control. This bit applies to DSP module (module 15). Assert local reset De-assert local reset Reserved Reserved NEXT 0-3h Module next state. SwRstDisable state SyncReset state Disable state Enable state Power and Sleep Controller (PSC) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 143: Psc1 Module Control N Register (Modules 0-31) (Mdctln)
Force is disabled. Force is enabled. 30-3 Reserved Reserved NEXT 0-3h Module next state. SwRstDisable state SyncReset state Disable state Enable state SPRUH90B – March 2013 Power and Sleep Controller (PSC) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 144: Power Management
................Power Consumption Overview .................. PSC and PLLC Overview ......................Features ..................Clock Management ................DSP Sleep Mode Management ........Additional Peripheral Power Management Considerations Power Management SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 145: Introduction
For detailed information on the PSC, see the Power and Sleep Controller (PSC) chapter. For detailed information on the PLLC, see the Device Clocking chapter and the Phase-Locked Loop Controller (PLLC) chapter. SPRUH90B – March 2013 Power Management Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 146: Features
Core Sleep Management DSP subsystem The DSP CPU can be put in sleep (IDLE) mode. Reduces the dynamic power. sleep mode Power Management SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 147: Clock Management
Furthermore, you can also power-down the PLL when bypassing it to minimize the overall power consumed by the PLL module. The Device Clocking chapter and the Phase-Locked Loop Controller (PLLC) chapter describe PLL bypass and PLL power down. SPRUH90B – March 2013 Power Management Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 148: Dsp Sleep Mode Management
SDRAM interface, it is recommended to use CLK1 as the source, as it allows maximal power savings (clock gating both VCLK/MCLK and EMB_CLK signal) via the PSC. Power Management SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 149: System Configuration (Syscfg) Module
System Configuration (SYSCFG) Module ........................... Topic Page ....................10.1 Introduction ....................... 10.2 Protection ..................10.3 Master Priority Control ..................... 10.4 Interrupt Support ................... 10.5 SYSCFG Registers SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 150: Introduction
• Several registers in the module are only accessible when the CPU requesting read/write access is in privileged mode. System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 151: Protection
Supervisor mode. The registers that can only be accessed in privileged mode are listed in Section 10.5. See the TMS320C674x DSP CPU and Instruction Set Reference Guide (SPRUFE8) for details on privilege levels. SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 152: Master Priority Control
Reserved PRU0 PRU1 TPCC0 11-15 Reserved TPTC0 - read TPTC0 - write TPTC1 - read TPTC1 - write 20-63 Reserved EMAC 65-255 Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 153: Interrupt Support
Either of the processors can set specific bits in this SYSCFG register, which in turn can interrupt the other processor, if the interrupts have been appropriately enabled in the processor’s interrupt controller. SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 154: Syscfg Registers
01C1 4170h SUSPSRC Suspend Source Register Section 10.5.11 01C1 4174h CHIPSIG Chip Signal Register Section 10.5.12 This register is for internal-use only. 154 System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 155: Revision Identification Register (Revid)
LEGEND: R = Read only; -n = value after reset Table 10-6. Device Identification Register 0 (DEVIDR0) Field Descriptions Field Value Description 31-0 DEVID0 R-0B7D F02Fh Device identification. SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 156: Boot Configuration Register (Bootcfg)
Table 10-8. Silicon Revision Identification Register (CHIPREVID) Field Descriptions Field Value Description 31-4 Reserved Reserved CHIPREV Identifies silicon revision of device. 0-3h Older silicon revision Silicon revision 3.0 System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 157: Kick Registers (Kick0R-Kick1R)
MMRs. The written data must be 95A4 F1E0h to unlock this register. KICK0R must be written before writing to the kick1 register. Writing any other value will lock the other MMRs. SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 158: Host 1 Configuration Register (Host1Cfg)
Reserved Reserved BOOTRDY DSP boot ready bit allowing DSP to boot. DSP held in reset mode. DSP released from wait in reset mode. System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 159: Interrupt Registers
Protection violation error. Reading this bit field reflects the raw status of the interrupt before enabling. Indicates the interrupt is not set. Writing 0 has no effect. Indicates the interrupt is set. Writing 1 sets the status. SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 160: Interrupt Enable Status/Clear Register (Ienstat)
Protection violation error. Reading this bit field reflects the interrupt enabled status. Indicates the interrupt is not set. Writing 0 has no effect. Indicates the interrupt is set. Writing 1 clears the status. System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 161: Interrupt Enable Register (Ienset)
Writing a 0 has not effect. Writing a 1 clears/disables this interrupt. PROTERR_CLR Protection violation error. Writing a 0 has not effect. Writing a 1 clears/disables this interrupt. SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 162: Fault Registers
LEGEND: R = Read only; -n = value after reset Table 10-17. Fault Address Register (FLTADDRR) Field Descriptions Field Value Description 31-0 FLTADDR 0-FFFF FFFFh Fault address for the first fault transfer. System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 163: Fault Status Register (Fltstat)
User write fault Reserved User read fault 5h-7h Reserved Supervisor execute fault 9h-Fh Reserved Supervisor write fault 11h-1Fh Reserved Supervisor read fault 21h-3Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 164: Master Priority Registers (Mstpri0-Mstpri2)
Reserved. Write the default value when modifying this register. Reserved Reserved. Always read as 0. Reserved Reserved. Write the default value when modifying this register. System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 165: Master Priority 1 Register (Mstpri1)
Reserved. Always read as 0. PRU0 0-7h PRU0 priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest). SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 166: Master Priority 2 Register (Mstpri2)
Reserved. Write the default value when modifying this register. EMAC 0-7h EMAC priority. Bit = 0 = priority 0 (highest); bit = 7h = priority 7 (lowest). System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 167: Pin Multiplexing Control Registers (Pinmux0-Pinmux19)
EMB_CLK Control Pin is 3-stated. Selects Function EMB_CLK from EMIFB LPSC (CLK1) Selects Function EMB_CLK from PLL DIV4P5 or SYSCLK5 (CLK2) 3h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 168 GPIO configuration for this pin has been completed. You should carefully consider the system implications of this pin being in an unknown state after reset. Reserved Selects Function GP7[14] 2h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 169: Pin Multiplexing Control 1 Register (Pinmux1)
Reserved Selects Function GP7[4] 9h-Fh Reserved 15-12 PINMUX1_15_12 EMB_A[1]/GP7[3] Control Pin is 3-stated. Selects Function EMB_A[1] 2h-7h Reserved Selects Function GP7[3] 9h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 170 2h-7h Reserved Selects Function GP7[1] 9h-Fh Reserved PINMUX1_3_0 EMB_BA[1]/GP7[0] Control Pin is 3-stated. Selects Function EMB_BA[1] 2h-7h Reserved Selects Function GP7[0] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 171: Pin Multiplexing Control 2 Register (Pinmux2)
Reserved Selects Function GP7[11] 9h-Fh Reserved 11-8 PINMUX2_11_8 EMB_A[8]/GP7[10] Control Pin is 3-stated. Selects Function EMB_A[8] 2h-7h Reserved Selects Function GP7[10] 9h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 172 2h-7h Reserved Selects Function GP7[9] 9h-Fh Reserved PINMUX2_3_0 EMB_A[6]/GP7[8] Control Pin is 3-stated. Selects Function EMB_A[6] 2h-7h Reserved Selects Function GP7[8] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 173: Pin Multiplexing Control 3 Register (Pinmux3)
Pin is 3-stated. 1h-Fh Reserved PINMUX3_7_4 — PINMUX3[7:4] Control Pin is 3-stated. 1h-Fh Reserved PINMUX3_3_0 — PINMUX3[3:0] Control Pin is 3-stated. 1h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 174: Pin Multiplexing Control 4 Register (Pinmux4)
Pin is 3-stated. 1h-Fh Reserved PINMUX4_7_4 — PINMUX4[7:4] Control Pin is 3-stated. 1h-Fh Reserved PINMUX4_3_0 — PINMUX4[3:0] Control Pin is 3-stated. 1h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 175: Pin Multiplexing Control 5 Register (Pinmux5)
Reserved Selects Function GP6[3] 9h-Fh Reserved 15-12 PINMUX5_15_12 EMB_D[2]/GP6[2] Control Pin is 3-stated. Selects Function EMB_D[2] 2h-7h Reserved Selects Function GP6[2] 9h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 176 EMB_D[0]/GP6[0] Control Pin is 3-stated. Selects Function EMB_D[0] 2h-7h Reserved Selects Function GP6[0] 9h-Fh Reserved PINMUX5_3_0 — PINMUX5[3:0] Control Pin is 3-stated. 1h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 177: Pin Multiplexing Control 6 Register (Pinmux6)
Reserved Selects Function GP6[11] 9h-Fh Reserved 15-12 PINMUX6_15_12 EMB_D[10]/GP6[10] Control Pin is 3-stated. Selects Function EMB_D[10] 2h-7h Reserved Selects Function GP6[10] 9h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 178 2h-7h Reserved Selects Function GP6[8] 9h-Fh Reserved PINMUX6_3_0 EMB_D[7]/GP6[7] Control Pin is 3-stated. Selects Function EMB_D[7] 2h-7h Reserved Selects Function GP6[7] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 179: Pin Multiplexing Control 7 Register (Pinmux7)
Selects Function GP5[2] 9h-Fh Reserved 19-16 PINMUX7_19_16 SPI0_SIMO[0]/EQEP0S/GP5[1]/BOOT[1] Control Pin is 3-stated. Selects Function SPI0_SIMO[0] Selects Function EQEP0S 3h-7h Reserved Selects Function GP5[1] 9h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 180 2h-7h Reserved Selects Function GP5[14] 9h-Fh Reserved PINMUX7_3_0 EMB_D[15]/GP6[15] Control Pin is 3-stated. Selects Function EMB_D[15] 2h-7h Reserved Selects Function GP6[15] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 181: Pin Multiplexing Control 8 Register (Pinmux8)
PINMUX8_15_12 UART0_RXD/I2C0_SDA/TM64P0_IN12/GP5[8]/BOOT[8] Control Pin is 3-stated. Selects Function UART0_RXD Selects Function I2C0_SDA Reserved Selects Function TM64P0_IN12 5h-7h Reserved Selects Function GP5[8] 9h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 182 Reserved Selects Function GP5[6] 9h-Fh Reserved PINMUX8_3_0 I2C1_SCL/GP5[5]/BOOT[5] Control Pin is 3-stated. Reserved Selects Function I2C1_SCL 3h-7h Reserved Selects Function GP5[5] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 183: Pin Multiplexing Control 9 Register (Pinmux9)
Selects Function GP2[13] 9h-Fh Reserved 15-12 PINMUX9_15_12 ACLKX0/ECAP0/APWM0/GP2[12] Control Pin is 3-stated. Selects Function ACLKX0 Selects Function ECAP0/APWM0 3h-7h Reserved Selects Function GP2[12] 9h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 184 PINMUX9[7:4] Control Pin is 3-stated. 1h-Fh Reserved PINMUX9_3_0 UART2_TXD/GP5[13] Control Pin is 3-stated. Reserved Selects Function UART2_TXD 3h-7h Reserved Selects Function GP5[13] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 185: Pin Multiplexing Control 10 Register (Pinmux10)
Selects Function GP3[4] 9h-Fh Reserved 19-16 PINMUX10_19_16 AXR0[3]/RMII_CRS_DV/GP3[3] Control Pin is 3-stated. Selects Function AXR0[3] Selects Function RMII_CRS_DV 3h-7h Reserved Selects Function GP3[3] 9h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 186 Pin is 3-stated. Selects Function AXR0[0] Selects Function RMII_TXD[0] 3h-7h Reserved Selects Function GP3[0] 9h-Fh Reserved PINMUX10_3_0 — PINMUX10[3:0] Control Pin is 3-stated. 1h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 187: Pin Multiplexing Control 11 Register (Pinmux11)
Reserved Selects Function GP3[14] 9h-Fh Reserved 19-16 PINMUX11_19_16 AXR0[11]/GP3[11] Control Pin is 3-stated. Selects Function AXR0[11] 2h-7h Reserved Selects Function GP3[11] 9h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 188 Selects Function GP3[8] 9h-Fh Reserved PINMUX11_3_0 AXR0[7]/MDIO_CLK/GP3[7] Control Pin is 3-stated. Selects Function AXR0[7] Selects Function MDIO_CLK 3h-7h Reserved Selects Function GP3[7] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 189: Pin Multiplexing Control 12 Register (Pinmux12)
Selects Function GP4[0] 9h-Fh Reserved 15-12 PINMUX12_15_12 AMUTE1/EHRPWMTZ/GP4[14] Control Pin is 3-stated. Selects Function AMUTE1 Selects Function EHRPWMTZ 3h-7h Reserved Selects Function GP4[14] 9h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 190 Pin is 3-stated. Selects Function ACLKR1 Selects Function ECAP2/APWM2 3h-7h Reserved Selects Function GP4[12] 9h-Fh Reserved PINMUX12_3_0 — PINMUX12[3:0] Control Pin is 3-stated. 1h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 191: Pin Multiplexing Control 13 Register (Pinmux13)
Selects Function GP4[8] 9h-Fh Reserved 15-12 PINMUX13_15_12 AXR1[7]/EPWM1B/GP4[7] Control Pin is 3-stated. Selects Function AXR1[7] Selects Function EPWM1B 3h-7h Reserved Selects Function GP4[7] 9h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 192 Selects Function GP4[5] 9h-Fh Reserved PINMUX13_3_0 AXR1[4]/EQEP1B/GP4[4] Control Pin is 3-stated. Selects Function AXR1[4] Selects Function EQEP1B 3h-7h Reserved Selects Function GP4[4] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 193: Pin Multiplexing Control 14 Register (Pinmux14)
Selects Function GP0[6] 9h-Fh Reserved 15-12 PINMUX14_15_12 EMA_D[5]/MMCSD_DAT[5]/GP0[5] Control Pin is 3-stated. Selects Function EMA_D[5] Selects Function MMCSD_DAT[5] 3h-7h Reserved Selects Function GP0[5] 9h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 194 Selects Function GP0[3] 9h-Fh Reserved PINMUX14_3_0 EMA_D[2]/MMCSD_DAT[2]/GP0[2] Control Pin is 3-stated. Selects Function EMA_D[2] Selects Function MMCSD_DAT[2] 3h-7h Reserved Selects Function GP0[2] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 195: Pin Multiplexing Control 15 Register (Pinmux15)
Pin is 3-stated. 1h-7h Reserved Selects Function GP0[14] 9h-Fh Reserved 15-12 PINMUX15_15_12 — GP0[13] Control Pin is 3-stated. 1h-7h Reserved Selects Function GP0[13] 9h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 196 Pin is 3-stated. 1h-7h Reserved Selects Function GP0[11] 9h-Fh Reserved PINMUX15_3_0 — GP0[10] Control Pin is 3-stated. 1h-7h Reserved Selects Function GP0[10] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 197: Pin Multiplexing Control 16 Register (Pinmux16)
Reserved Selects Function GP1[6] 9h-Fh Reserved 15-12 PINMUX16_15_12 EMA_A[5]/GP1[5] Control Pin is 3-stated. Selects Function EMA_A[5] 2h-7h Reserved Selects Function GP1[5] 9h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 198 Selects Function GP1[3] 9h-Fh Reserved PINMUX16_3_0 EMA_A[2]/MMCSD_CMD/GP1[2] Control Pin is 3-stated. Selects Function EMA_A[2] Selects Function MMCSD_CMD 3h-7h Reserved Selects Function GP1[2] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 199: Pin Multiplexing Control 17 Register (Pinmux17)
2h-7h Reserved Selects Function GP1[12] 9h-Fh Reserved PINMUX17_7_4 EMA_A[11]/GP1[11] Control Pin is 3-stated. Selects Function EMA_A[11] 2h-7h Reserved Selects Function GP1[11] 9h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 200 Table 10-39. Pin Multiplexing Control 17 Register (PINMUX17) Field Descriptions (continued) Field Ball Value Description PINMUX17_3_0 EMA_A[10]/GP1[10] Control Pin is 3-stated. Selects Function EMA_A[10] 2h-7h Reserved Selects Function GP1[10] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 201: Pin Multiplexing Control 18 Register (Pinmux18)
Pin is 3-stated. Selects Function EMA_CS[2] 2h-7h Reserved Selects Function GP2[5] 9h-Fh Reserved 11-8 PINMUX18_11_8 — PINMUX18[11:8] Control Pin is 3-stated. 1h-Fh Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 202: Pin Multiplexing Control 19 Register (Pinmux19)
Value Description 31-4 Reserved — — Reserved PINMUX19_3_0 EMA_WAIT[0]/GP2[10] Control Pin is 3-stated. Selects Function EMA_WAIT[0] 2h-7h Reserved Selects Function GP2[10] 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 203: Suspend Source Register (Suspsrc)
UART2 Emulation Suspend Source. No emulation suspend. DSP is the source of the emulation suspend. Reserved Reserved. Write the default value when modifying this register. SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 204 DSP is the source of the emulation suspend. ECAP0SRC ECAP0 Emulation Suspend Source. No emulation suspend. DSP is the source of the emulation suspend. System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 205: Chip Signal Register (Chipsig)
Asserts interrupt CHIPSIG2 Asserts SYSCFG_CHIPINT2 interrupt. No effect Asserts interrupt Reserved Reserved. Write the default value to all bits when modifying this register. SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 206: Chip Signal Clear Register (Chipsig_Clr)
Clears interrupt CHIPSIG2 Clears SYSCFG_CHIPINT2 interrupt. No effect Clears interrupt Reserved Reserved. Write the default value to all bits when modifying this register. System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 207: Chip Configuration 0 Register (Cfgchip0)
TC1 Default Burst Size (DBS). 16 bytes 32 bytes 64 bytes Reserved TC0DBS TC0 Default Burst Size (DBS). 16 bytes 32 bytes 64 bytes Reserved SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 208: Chip Configuration 1 Register (Cfgchip1)
EMAC C1 Miscellaneous Interrupt EMAC C2 RX Threshold Pulse Interrupt EMAC C2 RX Pulse Interrupt EMAC C2 TX Pulse Interrupt EMAC C2 Miscellaneous Interrupt 13h-1Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 209 13h-1Fh Reserved 16-15 Reserved Reserved. Write the default value to all bits when modifying this register. 14-13 Reserved Reserved. Always read as 0. SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 210 GPIO Interrupt from Bank 3 GPIO Interrupt from Bank 4 GPIO Interrupt from Bank 5 GPIO Interrupt from Bank 6 GPIO Interrupt from Bank 7 9h-Fh Reserved System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 211: Chip Configuration 3 Register (Cfgchip3)
Clock driven by DIV4.5 PLL output EMB_CLKSRC Clock source for EMIFB clock domain. Clock driven by PLLC SYSCLK5 Clock driven by DIV4.5 PLL output SPRUH90B – March 2013 System Configuration (SYSCFG) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 212: Chip Configuration 4 Register (Cfgchip4)
Clears the 'latched' GPIO interrupt for AMUTEIN of McASP1 when set to 1. No effect Clears interrupt AMUTECLR0 Clears the 'latched' GPIO interrupt for AMUTEIN of McASP0 when set to 1. No effect Clears interrupt System Configuration (SYSCFG) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 213: Boot Considerations
Chapter 11 SPRUH90B – March 2013 Boot Considerations ........................... Topic Page ....................11.1 Introduction SPRUH90B – March 2013 Boot Considerations Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 214: Introduction
See Using the C6747/45/43 Bootloader Application Report (SPRABB1) for more details on the ROM Boot Loader, a list of boot pins used, and the complete list of supported boot modes. Boot Considerations SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 215: Programmable Real-Time Unit Subsystem (Pruss)
The PRUSS documentation (peripheral guide) is on the external wiki: Programmable_Realtime_Unit. SPRUH90B – March 2013 Programmable Real-Time Unit Subsystem (PRUSS) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 216: Enhanced Capture (Ecap) Module
The enhanced capture (eCAP) module is essential in systems where accurate timing of external events is important. This chapter describes the eCAP module..........................Topic Page ....................13.1 Introduction ....................13.2 Architecture ....................13.3 Applications ......................13.4 Registers Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 217: Introduction
All above resources dedicated to a single input pin • When not used in capture mode, the ECAP module can be configured as a single channel PWM output SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 218: Architecture
SyncIn ECAP1 ECAP1 module ECAP1INT SyncOut SyncIn ECAP2/ ECAP2 APWM2 GPIO Interrupt module Controller ECAP2INT SyncOut SyncIn ECAPx/ ECAPx APWMx module ECAPxINT SyncOut Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 219: Capture And Apwm Operating Mode
(2) In APWM mode, writing any value to CAP1/CAP2 active registers also writes the same value to the corresponding shadow registers CAP3/CAP4. This emulates immediate mode. Writing to the shadow registers CAP3/CAP4 invokes the shadow mode. SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 220: Capture Mode Description
Continuous / to Interrupt Trigger Oneshot Controller CTR_OVF Capture Control Flag CTR=PRD control CTR=CMP ECCTL2 [ RE-ARM, CONT/ONESHT, STOP_WRAP] Registers: ECEINT, ECFLG, ECCLR, ECFRC Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 221: Event Prescale Control
Figure 13-5. Prescale Function Waveforms ECAPx PSout div 2 PSout div 4 PSout div 6 PSout div 8 PSout div 10 SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 222: Continuous/One-Shot Block Diagram
Figure 13-6. Continuous/One-shot Block Diagram 2:4 MUX CEVT1 CEVT2 Modulo 4 CEVT3 Stop counter CEVT4 Mod_eq One−shot control logic Stop value (2b) ECCTL2[STOP_WRAP] ECCTL2[RE−ARM] ECCTL2[CONT/ONESHT] Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 223: Counter And Synchronization Block Diagram
Figure 13-7. Counter and Synchronization Block Diagram SYNC ECCTL2[SWSYNC] ECCTL2[SYNCOSEL] SYNCI CTR=PRD Disable SYNCO Disable ECCTL2[SYNCI_EN] Sync out select CTRPHS LD_CTRPHS Delta−mode TSCTR (counter 32b) SYSCLK CTR−OVF CTR[31−0] SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 224 (ECCTL2[CAP/APWM == 0]). The CTR = PRD, CTR = CMP flags are only valid in APWM mode (ECCTL2[CAP/APWM == 1]). CNTOVF flag is valid in both modes. Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 225: Interrupts In Ecap Module
ECEINT CEVT4 ECFLG Clear ECCLR ECFRC Latch CTROVF ECEINT ECFLG Clear ECCLR ECFRC Latch ECEINT PRDEQ ECFLG Clear ECCLR ECFRC Latch ECEINT CMPEQ SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 226: Pwm Waveform Details Of Apwm Mode Operation
CMP = 0x00000002, output low 2 cycles CMP = PERIOD, output low except for 1 cycle (<100% duty) CMP = PERIOD+1, output low for complete period (100% duty) Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 227: Applications
// CAP/APWM mode bit #define EC_CAP_MODE #define EC_APWM_MODE // APWMPOL bit #define EC_ACTV_HI #define EC_ACTV_LO // Generic #define EC_DISABLE #define EC_ENABLE #define EC_FORCE SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 228: Absolute Time-Stamp Operation Rising Edge Trigger Example
CTR[0−31] 00000000 MOD4 CAP1 CAP2 CAP3 CAP4 All capture values valid Polarity selection (can be read) at this time Capture registers [1−4] 228 Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 229: Ecap Initialization For Cap Mode Absolute Time, Rising Edge Trigger
// Fetch Time-Stamp captured at t4 Period1 = TSt2-TSt1; // Calculate 1st period Period2 = TSt3-TSt2; // Calculate 2nd period Period3 = TSt4-TSt3; // Calculate 3rd period SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 230: Absolute Time-Stamp Operation Rising And Falling Edge Trigger Example
CEVT2 CEVT4 CEVT1 CEVT3 CEVT1 CEVT3 CEVT1 CAPx pin FFFFFFFF CTR[0−31] 00000000 MOD4 CAP1 CAP2 CAP3 CAP4 Polarity selection Capture registers [1−4] 230 Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 231: Ecap Initialization For Cap Mode Absolute Time, Rising And Falling Edge Trigger
// Fetch Time-Stamp captured at t4 Period1 = TSt3-TSt1; // Calculate 1st period DutyOnTime1 = TSt2-TSt1; // Calculate On time DutyOffTime1 = TSt3-TSt2; // Calculate Off time SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 232: Time Difference (Delta) Operation Rising Edge Trigger Example
CTR value at CEVT1 CAP2 CAP3 CAP4 Polarity selection Capture registers [1−4] All capture values valid (can be read) at this time 232 Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 233: Ecap Initialization For Cap Mode Delta Time, Rising Edge Trigger
// Fetch Time-Stamp captured at T2 Period2 = ECAPxRegs.CAP3; // Fetch Time-Stamp captured at T3 Period3 = ECAPxRegs.CAP4; // Fetch Time-Stamp captured at T4 SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 234: Time Difference (Delta) Operation Rising And Falling Edge Trigger Example
CEVT1 CEVT3 CEVT5 CAPx pin FFFFFFFF CTR[0−31] 00000000 MOD4 CAP1 CTR value at CEVT1 CAP2 CAP3 CAP4 Polarity selection Capture registers [1−4] 234 Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 235: Ecap Initialization For Cap Mode Delta Time, Rising And Falling Edge Triggers
// Fetch Time-Stamp captured at T4 DutyOffTime2 = ECAPxRegs.CAP1; // Fetch Time-Stamp captured at T1 Period1 = DutyOnTime1 + DutyOffTime1; Period2 = DutyOnTime2 + DutyOffTime2; SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 236: Application Of The Apwm Mode
Figure 13-14. PWM Waveform Details of APWM Mode Operation TSCTR FFFFFFFF 1000h APRD 500h ACMP 300h 0000000C APWMx (o/p pin) Off−time Period time 236 Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 237: Ecap Initialization For Apwm Mode
(F1 = 1/20,000) requirement. Here Slave2 Freq = 2 × F1, Slave3 Freq = 4 × F1 and Slave4 Freq = 5 × F1. Note here values are in decimal notation. Also, only the APWM1 output waveform is shown. SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 238: Multichannel Pwm Example Using 4 Ecap Modules
7,000 ACMP(1) 0000 0000 APWM1 (o/p pin) CTR=PRD (SyncOut) Time Phase = 0° Slave APWM(2−4) module/s 10,000 APRD(2) 5,000 APRD(3) 4,000 APRD(4) Time Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 239: Ecap1 Initialization For Multichannel Pwm Generation With Synchronization
Table 13-9. ECAP4 Initialization for Multichannel PWM Generation with Synchronization Register Value CAP1 CAP1 4000 CTRPHS CTRPHS ECCTL2 CAP_APWM EC_APWM_MODE ECCTL2 APWMPOL EC_ACTV_HI ECCTL2 SYNCI_EN EC_ENABLE ECCTL2 SYNCO_SEL EC_SYNCO_DIS ECCTL2 TSCTRSTOP EC_RUN SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 240 (Legs). Note eCAP1 module is the Master and issues a sync out pulse to the slaves (modules 2, 3) whenever TSCTR = Period value. Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 241: Multiphase (Channel) Interleaved Pwm Example Using 3 Ecap Modules
APWM1 APWM2 APWM3 Vout TSCTR 1200 APRD(1) APRD(1) SYNCO pulse (CTR=PRD) APWM1 Φ2=120° CTRPHS(2)=800 APWM2 Φ3=240° CTRPHS(3)=400 APWM3 SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 242: Ecap1 Initialization For Multichannel Pwm Generation With Phase Control
ECAP2Regs.CAP2 = 700; // Set Duty cycle i.e. compare value = 700 ECAP3Regs.CAP2 = 700; // Set Duty cycle i.e. compare value = 700 Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 243: Registers
Table 13-14. Time-Stamp Counter Register (TSCTR) Field Descriptions Field Value Description 31-0 TSCTR 0-FFFF FFFFh Active 32-bit counter register that is used as the capture time-base SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 244: Counter Phase Control Register (Ctrphs)
• Time-Stamp (i.e., counter value) during a capture event • Software - may be useful for test purposes • APRD active register when used in APWM mode Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 245: Capture 2 Register (Cap2)
In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period shadow (APRD) register. You update the PWM period value through this register. In this mode, CAP3 shadows CAP1. SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 246: Capture 4 Register (Cap4)
Enable Loading of CAP1-4 registers on a capture event Disable CAP1-4 register loads at capture event time. Enable CAP1-4 register loads at capture event time. Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 247 Capture Event 1 Polarity select Capture Event 1 triggered on a rising edge (RE) Capture Event 1 triggered on a falling edge (FE) SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 248: Ecap Control Register 2 (Ecctl2)
Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event. TSCTRSTOP Time Stamp (TSCTR) Counter Stop (freeze) Control TSCTR stopped TSCTR free-running Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 249: Ecap Interrupt Enable Register (Eceint)
3. Disable eCAP interrupts 4. Configure peripheral registers 5. Clear spurious eCAP interrupt flags 6. Enable eCAP interrupts 7. Start eCAP counter 8. Enable global interrupts SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 250: Ecap Interrupt Enable Register (Eceint)
Capture Event 1 Interrupt Enable Disable Capture Event 1 as an Interrupt source Enable Capture Event 1 as an Interrupt source Reserved Reserved Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 251: Ecap Interrupt Flag Register (Ecflg)
Indicates no event occurred. Indicates the first event occurred at ECAPn pin. Global Interrupt Status Flag Indicates no interrupt generated. Indicates that an interrupt was generated. SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 252: Ecap Interrupt Clear Register (Ecclr)
Writing a 1 clears the INT flag and enable further interrupts to be generated if any of the event flags are set to 1. Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 253: Ecap Interrupt Forcing Register (Ecfrc)
Writing a 1 sets the CEVT2 flag bit. CEVT1 Force Capture Event 1 No effect. Always reads back a 0. Writing a 1 sets the CEVT1 flag bit. Reserved Reserved SPRUH90B – March 2013 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 254: Revision Id Register (Revid)
LEGEND: R = Read only; -n = value after reset Table 13-26. Revision ID Register (REVID) Field Descriptions Field Value Description 31-0 44D2 2100h Revision ID. Enhanced Capture (eCAP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 255: Enhanced High-Resolution Pulse-Width Modulator (Ehrpwm)
This chapter describes the enhanced high-resolution pulse-width modulator (eHRPWM)..........................Topic Page ....................14.1 Introduction ....................14.2 Architecture ..............14.3 Applications to Power Topologies ......................14.4 Registers SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 256: Introduction
Each ePWM module consists of seven submodules and is connected within a system via the signals shown in Figure 14-2. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 257: Multiple Epwm Modules
To eCAP1 SYNCI EPWM2INT EPWM2A Interrupt GPIO ePWM2 module EPWM2B Controller SYNCO SYNCI EPWMxINT EPWMxA ePWMx module EPWMxB SYNCO Peripheral Frame 1 SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 258: Submodules And Signal Connections For An Epwm Module
Figure 14-3 also shows the key internal submodule interconnect signals. Each submodule is described in detail in Section 14.2. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 259: Epwm Submodules And Critical Internal Signal Interconnects
CTR = CMPB band chopper zone (DB) (PC) (TZ) EPWMB EPWMxB CMPB active (16) EPWMxTZINT CMPB shadow (16) CTR = 0 TZ1 to TZn SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 260: Register Mapping
These registers are only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, these locations are reserved. See your device-specific data manual to determine which instances include the HRPWM. 260 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 261: Architecture
• Duty cycle of the second and subsequent pulses. • Bypass the PWM-chopper module entirely. In this case the PWM waveform is passed through without modification. SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 262 • Poll, set, or clear event flags High-Resolution PWM Section 14.2.10 • Enable extended time resolution capabilities (HRPWM) • Configure finer time granularity control or edge positioning Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 263 // = = = = = = = = = = = = = = = = = = = = = = = = = = // CHPEN bit #define CHP_DISABLE #define CHP_ENABLE SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 264: Proper Interrupt Initialization Procedure
2. Disable ePWM interrupts 3. Initialize peripheral registers 4. Clear any spurious ePWM flags 5. Enable ePWM interrupts 6. Enable global interrupts Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 265: Time-Base (Tb) Submodule
Configure the rate of the time-base clock; a prescaled version of the CPU system clock (SYSCLKOUT). This allows the time-base counter to increment/decrement at a slower rate. SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 266: Time-Base Submodule Signals And Registers
EPWMxSYNCO CTR = CMPB TBCTL[PHSEN] TBCNT Select Counter Active Reg Disable TBPHS TBCTL[SYNCOSEL] Phase Active Reg Clock SYSCLKOUT TBCLK Prescale TBCTL[HSPCLKDIV] TBCTL[CLKDIV] Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 267: Key Time-Base Signals
When it reaches zero, the time-base counter is reset to the period value and it begins to decrement once again. SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 268: Time-Base Frequency And Period
Time-Base Period Immediate Load Mode: If immediate load mode is selected (TBCTL[PRDLD] = 1), then a read from or a write to the TBPRD memory address goes directly to the active register. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 269: Time-Base Counter Synchronization Scheme
14-7. Figure 14-7. Time-Base Counter Synchronization Scheme 1 GPIO MUX EPWM1SYNCI ePWM1 EPWM1SYNCO EPWM2SYNCI ePWM2 EPWM2SYNCO EPWM3SYNCI ePWM3 EPWM3SYNCO EPWMxSYNCI ePWMx EPWMxSYNCO SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 270 To illustrate the operation of the first three modes, Figure 14-8 Figure 14-11 show when events are generated and how the time-base responds to an EPWMxSYNCI signal. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 271: Time-Base Up-Count Mode Waveforms
Figure 14-8. Time-Base Up-Count Mode Waveforms TBCNT FFFFh TBPRD (value) TBPHS (value) 0000h EPWMxSYNCI CTR_dir CTR = 0 CTR = PRD CNT_max SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 272: Time-Base Down-Count Mode Waveforms
Figure 14-10. Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down on Synchronization Event TBCNT FFFFh TBPRD (value) TBPHS (value) 0000h EPWMxSYNCI CTR_dir DOWN DOWN DOWN CTR = 0 CTR = PRD CNT_max Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 273: Time-Base Up-Down Count Waveforms, Tbctl[Phsdir = 1] Count Up On Synchronization Event
Figure 14-11. Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up on Synchronization Event TBCNT FFFFh TBPRD (value) TBPHS (value) 0000h EPWMxSYNCI CTR_dir DOWN DOWN DOWN CTR = 0 CTR = PRD CNT_max SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 274: Counter-Compare (Cc) Submodule
B Shadow CMPB CTR = PRD CMPCTL[SHDWBFULL] load Compare B Active Reg. CTR = 0 CMPB CMPCTL[SHDWBMODE] Compare B Shadow Reg. CMPCTL[LOADBMODE] Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 275: Counter-Compare Submodule Registers
CTR = 0 Time-base counter equal to zero. TBCNT = 0000h Used to load active counter-compare A and B registers from the shadow register SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 276 To best illustrate the operation of the first three modes, the timing diagrams in Figure 14-14 Figure 14- show when events are generated and how the EPWMxSYNCI signal interacts. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 277: Counter-Compare Event Waveforms In Up-Count Mode
Figure 14-15. Counter-Compare Events in Down-Count Mode TBCNT FFFFh TBPRD (value) CMPA (value) CMPB (value) TBPHS (value) 0000h EPWMxSYNCI CTR = CMPA CTR = CMPB SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 278: Counter-Compare Events In Up-Down-Count Mode, Tbctl[Phsdir = 0] Count Down On Synchronization Event
Figure 14-17. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up on Synchronization Event TBCNT FFFFh TBPRD (value) CMPA (value) CMPB (value) TBPHS (value) 0000h EPWMxSYNCI CTR = CMPB CTR = CMPA Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 279: Action-Qualifier (Aq) Submodule
Action-Qualifier Control Register For Output A (EPWMxA) AQCTLB Action-Qualifier Control Register For Output B (EPWMxB) AQSFRC Action-Qualifier Software Force Register AQCSFRC Action-Qualifier Continuous Software Force SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 280: Action-Qualifier Submodule Inputs And Outputs
Nothing" option prevents an event from causing an action on the EPWMxA and EPWMxB outputs, this event can still trigger interrupts. See the event-trigger submodule description in Section 14.2.9 details. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 281: Possible Action-Qualifier Actions For Epwmxa And Epwmxb Outputs
Figure 14-20. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs TB Counter equals: Actions force Comp Comp Zero Period Do Nothing Clear Low Set High Toggle SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 282: Action-Qualifier Event Priority For Up-Down-Count Mode
Counter equal to Zero Counter equal to CMPB on down-count (CBD) Counter equal to CMPA on down-count (CAD) 5 (Lowest) Counter equal to period (TBPRD) Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 283: Behavior If Cmpa/Cmpb Is Greater Than The Period
TBPRD. Use the Zero action to set the PWM and a compare-up action to clear the PWM. Modulate the compare value from 0 to TBPRD+1 to achieve 0-100% PWM duty. SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 284: Up-Down-Count Mode Symmetrical Waveform
EPWMxA/EPWMxB CMPA = 2, 50% Duty Case 3: EPWMxA/EPWMxB CMPA = 1, 75% Duty Case 4: EPWMxA/EPWMxB CMPA = 0, 100% Duty Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 285: Up, Single Edge Asymmetric Waveform, With Independent Modulation On Epwmxa And Epwmxb-Active High
(5) Actions at zero and period, although appearing to occur concurrently, are actually separated by one TBCLK period. TBCNT wraps from period to 0000h. SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 286: Epwmx Initialization For
Table 14-14. EPWMx Run Time Changes for Figure 14-22 Register Value Comments CMPA CMPA Duty1A Adjust duty for output EPWM1A CMPB CMPB Duty1B Adjust duty for output EPWM1B Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 287: Up, Single Edge Asymmetric Waveform With Independent Modulation On Epwmxa And Epwmxb-Active Low
(5) Actions at zero and period, although appearing to occur concurrently, are actually separated by one TBCLK period. TBCNT wraps from period to 0000h. SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 288: Epwmx Initialization For
Table 14-16. EPWMx Run Time Changes for Figure 14-23 Register Value Comments CMPA CMPA Duty1A Adjust duty for output EPWM1A CMPB CMPB Duty1B Adjust duty for output EPWM1B Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 289: Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation On Epwmxa
(4) EPWMxB can be used to generate a 50% duty square wave with frequency = 1/2 × ((TBPRD + 1) × TBCLK) SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 290: Epwmx Initialization For
Table 14-18. EPWMx Run Time Changes for Figure 14-24 Register Value Comments CMPA CMPA EdgePosA Adjust duty for output EPWM1A CMPB CMPB EdgePosB Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 291: Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation On Epwmxa And Epwmxb - Active Low
(3) Duty modulation for EPWMxB is set by CMPB and is active low (that is, the low time duty is proportional to CMPB). (4) Outputs EPWMxA and EPWMxB can drive independent power switches SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 292: Epwmx Initialization For
Table 14-20. EPWMx Run Time Changes for Figure 14-25 Register Value Comments CMPA CMPA Duty1A Adjust duty for output EPWM1A CMPB CMPB Duty1B Adjust duty for output EPWM1B Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 293: Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation On Epwmxa And Epwmxb - Complementary
(5) Dead-band = CMPB - CMPA (fully programmable edge placement by software). Note the dead-band module is also available if the more classical edge delay method is required. SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 294: Epwmx Initialization For
Table 14-22. EPWMx Run Time Changes for Figure 14-26 Register Value Comments CMPA CMPA Duty1A Adjust duty for output EPWM1A CMPB CMPB Duty1B Adjust duty for output EPWM1B Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 295: Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation On Epwmxa-Active Low
(5) To change this example to active high, CMPA and CMPB actions need to be inverted (i.e., Set ! Clear and Clear Set). (6) Duty modulation for EPWMxB is fixed at 50% (utilizes spare action resources for EPWMxB) SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 296: Epwmx Initialization For
Table 14-24. EPWMx Run Time Changes for Figure 14-27 Register Value Comments CMPA CMPA EdgePosA Adjust duty for output EPWM1A CMPB CMPB EdgePosB Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 297: Dead-Band Generator (Db) Submodule
Register Description Address Offset Shadowed DBCTL Dead-Band Control Register DBRED Dead-Band Rising Edge Delay Count Register DBFED Dead-Band Falling Edge Delay Count Register SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 298: Configuration Options For The Dead-Band Generator Submodule
0 S1 Rising edge EPWMxA delay EPWMxA in (10-bit counter) Falling edge 0 S3 delay EPWMxB (10-bit counter) DBCTL[IN_MODE] DBCTL[POLSEL] DBCTL[OUT_MODE] EPWMxB in Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 299: Classical Dead-Band Operating Modes
These are classical dead-band modes and assume that DBCTL[IN_MODE] = 0,0. That is, EPWMxA in is the source for both the falling-edge and rising-edge delays. Enhanced, non-traditional modes can be achieved by changing the IN_MODE configuration. SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 300: Dead-Band Waveforms For Typical Cases (0% < Duty < 100%)
FED = DBFED × T TBCLK RED = DBRED × T TBCLK Where T is the period of TBCLK, the prescaled version of SYSCLKOUT. TBCLK Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 301: Pwm-Chopper (Pc) Submodule
The PWM-chopper submodule operation is controlled via the register in Table 14-27. Table 14-27. PWM-Chopper Submodule Registers Acronym Register Description Address Offset Shadowed PCCTL PWM-chopper Control Register SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 302: Pwm-Chopper Submodule Signals And Registers
SYSCLKOUT PCCTL [OSHTWTH] PCCTL Divider and PSCLK [CHPEN] duty control PCCTL [OSHTWTH] PCCTL[CHPFREQ] PCCTL[CHPDUTY] Pulse-width PWMB_ch EPWMxB shot OSHT EPWMxA Start Bypass Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 303: Simple Pwm-Chopper Submodule Waveforms Showing Chopping Action Only
Figure 14-34. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses Start OSHT pulse EPWMxA in PSCLK Prog. pulse width (OSHTWTH) OSHT EPWMxA out Sustaining pulses SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 304: Pwm-Chopper Submodule Waveforms Showing The Pulse Width (Duty Cycle) Control Of Sustaining Pulses
Figure 14-35. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining Pulses PSCLK PSCLK period PSCLK Period 62.5% 87.5% 37.5% 12.5% Duty Duty Duty Duty Duty Duty Duty Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 305: Trip-Zone (Tz) Submodule
Interrupt generation is possible on any trip-zone pin. • Software-forced tripping is also supported. • The trip-zone submodule can be fully bypassed if it is not required. SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 306: Trip-Zone Submodule Registers
TZCTL[TZA] and TZCTL[TZB] register bits. One of four possible actions, shown in Table 14-29, can be taken on a trip event. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 307: Possible Actions On A Trip Event
– TZCTL[TZB] = 3: EPWM1B will ignore the trip event. 14.2.8.4 Generating Trip Event Interrupts Figure 14-37 Figure 14-38 illustrate the trip-zone submodule control and interrupt logic, respectively. SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 308: Trip-Zone Submodule Mode Control Logic
TZCLR[CBC] Latch Latch trip event TZEINT[CBC] TZFLG[OST] Generate EPWMxTZINT interrupt Clear TZCLR[OST] (Interrupt controller) pulse when input=1 Latch OSHT trip event TZEINT[OST] Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 309: Event-Trigger (Et) Submodule
Address Offset Shadowed ETSEL Event-Trigger Selection Register ETPS Event-Trigger Prescale Register ETFLG Event-Trigger Flag Register ETCLR Event-Trigger Clear Register ETFRC Event-Trigger Force Register SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 310: Event-Trigger Submodule Inter-Connectivity To Interrupt Controller
CTR = CMPA CTRD=CMPA Direction ETPS reg CTRU=CMPB qualifier count CTR = CMPB CTRD=CMPB ETFLG reg clear ETCLR reg CTR_dir count ETFRC reg Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 311 INTCNT. The counter will behave as described above when INTCNT = INTPRD. When INTPRD = 0, the counter is disabled and hence no events will be detected and the ETFRC[INT] bit is also ignored. SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 312: Event-Trigger Interrupt Generator
Clear CNT pulse EPWMxINT 2-bit when ETFRC[INT] Counter input = 1 CTR=0 CTR=PRD Inc CNT CTRU=CMPA CTRD=CMPA ETSEL[INT] CTRU=CMPB CTRD=CMPB ETPS[INTPRD] Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 313: High-Resolution Pwm (Hrpwm) Submodule
CTR = CMPB band chopper zone (DB) (PC) (TZ) EPWMB EPWMxB CMPB active (16) EPWMxTZINT CMPB shadow (16) TZ1 to TZn CTR = 0 SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 314: Resolution Calculations For Conventionally Generated Pwm
Single-phase buck, boost, and flyback • Multi-phase buck, boost, and flyback • Phase-shifted full bridge • Direct modulation of D-Class power amplifiers Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 315: Operating Logic Using Mep
Register Description Address Offset Shadowed TBPHSHR Extension Register for HRPWM Phase CMPAHR Extension Register for HRPWM Duty HRCNFG HRPWM Configuration Register 1040h SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 316: Relationship Between Mep Steps, Pwm Frequency And Resolution
PWM minimum frequency is based on a maximum period value, TBPRD = 65 535. PWM mode is asymmetrical up-count. Resolution in bits is given for the maximum PWM frequency stated. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 317: Required Pwm Waveform For A Requested Duty
For a PWM Period register value of 80 counts, PWM Period = 80 × 10 ns = 800 ns, PWM frequency = 1/800 ns = 1.25 MHz Assumed MEP step size for the above example = 180 ps SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 318 = 5632 + 180h = 1600h + 180h CMPAHR value = 1780h; CMPAHR value = 1700h, lower 8 bits will be ignored by hardware. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 319: Low % Duty Cycle Range Limitation Example When Pwm Frequency = 1 Mhz
14-48. In this case low percent duty limitation is no longer an issue. Figure 14-48. High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz EPWM1A SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 320: Applications To Power Topologies
Figure 14-49. Simplified ePWM Module SyncIn Phase reg EPWMxA Φ=0° EPWMxB CTR = 0 CTR=CMPB SyncOut Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 321: Key Configuration Capabilities
Ext SyncIn (optional) Master Slave Phase reg SyncIn SyncIn Phase reg Φ=0° Φ=0° EPWM2A EPWM1A EPWM1B EPWM2B CTR=0 CTR=0 CTR=CMPB CTR=CMPB SyncOut SyncOut SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 322: Controlling Multiple Buck Converters With Independent Frequencies
EPWM4A Φ=X Buck #4 EPWM4B CTR=0 EPWM4A CTR=CMPB SyncOut NOTE: Θ = X indicates value in phase register is a "don't care" Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 323: Buck Waveforms For
Figure 14-52. Buck Waveforms for Figure 14-51 (Note: Only three bucks shown here) 1200 EPWM1A 1400 EPWM2A EPWM3A Indicates this event triggers an interrupt SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 324: Epwm1 Initialization For
SHDWAMODE CC_SHADOW SHDWBMODE CC_SHADOW LOADAMODE CC_CTR_ZERO Load on CTR = 0 LOADBMODE CC_CTR_ZERO Load on CTR = 0 AQCTLA AQ_CLEAR AQ_SET 324 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 325: Controlling Multiple Buck Converters With Same Frequencies
EPWM1B SyncOut Vin3 Vout3 Buck #3 Slave Phase reg EPWM2A SyncIn Φ=X EPWM2A Vin4 Vout4 EPWM2B CTR=0 CTR=CMPB Buck #4 SyncOut EPWM2B SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 326: Pwm2 Pwm1
Applications to Power Topologies www.ti.com Figure 14-54. Buck Waveforms for Figure 14-53 (Note: F PWM2 PWM1 EPWM1A EPWM1B EPWM2A EPWM2B 326 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 327: Epwm1 Initialization For
// adjust duty for output EPWM1B EPwm2Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM2A EPwm2Regs.CMPB = 300; // adjust duty for output EPWM2B SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 328: Controlling Multiple Half H-Bridge (Hhb) Converters
EPWM1A EPWM1A Φ=0° EPWM1B CTR=0 CTR=CMPB EPWM1B SyncOut Slave Phase reg SyncIn DC_bus EPWM2A out2 Φ=0° EPWM2B CTR=0 EPWM2A CTR=CMPB SyncOut EPWM2B Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 329 Applications to Power Topologies www.ti.com Figure 14-56. Half-H Bridge Waveforms for Figure 14-55 (Note: F PWM2 PWM1 EPWM1A EPWM1B Pulse Center EPWM2A EPWM2B Pulse Center SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 330: Epwm1 Initialization For
// adjust duty for output EPWM1B EPwm2Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM2A EPwm2Regs.CMPB = 250; // adjust duty for output EPWM2B Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 331: Controlling Dual 3-Phase Inverters For Motors (Aci And Pmsm)
CTR=CMPB EPWM4B EPWM5B EPWM6B 3 phase motor SyncOut Slave Phase reg SyncIn 3 phase inverter #2 Φ=0° EPWM6A EPWM6B CTR=0 CTR=CMPB SyncOut SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 332 Figure 14-58. 3-Phase Inverter Waveforms for Figure 14-57 (Only One Inverter Shown) EPWM1A EPWM1B Φ2=0 EPWM2A EPWM2B Φ3=0 EPWM3A EPWM3B 332 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 333: Epwm1 Initialization For
DBCTL MODE DB_FULL_ENABLE Enable Dead-band module POLSEL DB_ACTV_HIC Active Hi complementary DBFED DBFED FED = 50 TBCLKs DBRED RED = 50 TBCLKs SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 334: Epwm3 Initialization For
EPwm1Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM1A EPwm2Regs.CMPA.half.CMPA = 600; // adjust duty for output EPWM2A EPwm3Regs.CMPA.half.CMPA = 700; // adjust duty for output EPWM3A Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 335: Practical Applications Using Phase Control Between Pwm Modules
SyncIn pulse (CTR = PRD), the value of TBPHS = 200 is loaded into the slave TBCNT register so the slave time-base is always leading the master's time-base by 120°. SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 336: Controlling A 3-Phase Interleaved Dc/Dc Converter
TBPHS(3,3) = (600/3) × (3 - 1) = 200 × 2 = 400 (Phase value for Slave module 3) Figure 14-62 shows the waveforms for the configuration in Figure 14-61. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 337: Control Of A 3-Phase Interleaved Dc/Dc Converter
EPWM2B EPWM3B Phase reg SyncIn EPWM2A Φ=120° Φ=120° EPWM2B CTR=0 CTR=CMPB SyncOut Slave Phase reg SyncIn EPWM3A Φ=240° EPWM3B CTR=0 CTR=CMPB SyncOut SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 338 Figure 14-62. 3-Phase Interleaved DC/DC Converter Waveforms for Figure 14-61 EPWM1A EPWM1B Φ2=120° TBPHS (=300) EPWM2A EPWM2B Φ2=120° TBPHS (=300) EPWM3A EPWM3B 338 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 339: Epwm1 Initialization For
DBCTL MODE DB_FULL_ENABLE Enable Dead-band module POLSEL DB_ACTV_HIC Active Hi complementary DBFED DBFED FED = 20 TBCLKs DBRED RED = 20 TBCLKs SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 340: Epwm3 Initialization For
// adjust duty for output EPWM1A EPwm2Regs.CMPA.half.CMPA = 285; // adjust duty for output EPWM2A EPwm3Regs.CMPA.half.CMPA = 285; // adjust duty for output EPWM3A Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 341: Controlling Zero Voltage Switched Full Bridge (Zvsfb) Converter
EPWM1A EPWM1B CTR=0 CTR=CMPB EPWM1A EPWM2A SyncOut Slave Phase reg SyncIn EPWM2A Φ=Var° EPWM1B EPWM2B EPWM2B CTR=0 CTR=CMPB SyncOut Var = Variable SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 342: Zvs Full-H Bridge Waveforms
Figure 14-64. ZVS Full-H Bridge Waveforms 1200 EPWM1A ZVS transition Power phase EPWM1B ZVS transition Φ2=variable TBPHS =(1200−Φ2) EPWM2A EPWM2B Power phase 342 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 343: Epwm1 Initialization For
EPwm1Regs.DBRED = RED1_NewValue; // Update ZVS transition interval EPwm2Regs.DBFED = FED2_NewValue; // Update ZVS transition interval EPwm2Regs.DBRED = RED2_NewValue; // Update ZVS transition interval SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 344: Registers
PRDLD PHSEN CTRMODE R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-3h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 345: Time-Base Control Register (Tbctl) Field Descriptions
CTR = 0: Time-base counter equal to zero (TBCNT = 0000h) CTR = CMPB : Time-base counter equal to counter-compare B (TBCNT = CMPB) Disable EPWMxSYNCO signal SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 346: Time-Base Status Register (Tbsts)
To make this bit meaningful, you must first set the appropriate mode via TBCTL[CTRMODE]. Time-Base Counter is currently counting down. Time-Base Counter is currently counting up. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 347: Time-Base Phase Register (Tbphs)
Writing to these bits sets the current time-base counter value. The update happens as soon as the write occurs; the write is NOT synchronized to the time-base clock (TBCLK) and the register is not shadowed. SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 348: Counter-Compare Submodule Registers
This register is only available on ePWM instances that include the high-resolution PWM (HRPWM) extension; otherwise, this location is reserved. See your device-specific data manual to determine which instances include the HRPWM. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 349: Counter-Compare Control Register (Cmpctl)
Load on CTR = PRD: Time-base counter equal to period (TBCNT = TBPRD) Load on either CTR = 0 or CTR = PRD Freeze (no loads possible) SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 350: Counter-Compare A Register (Cmpa)
• In either mode, the active and shadow registers share the same memory map address. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 351: Action-Qualifier Submodule Registers
Action-Qualifier Output B Control Register Section 14.4.3.2 AQSFRC Action-Qualifier Software Force Register Section 14.4.3.3 AQCSFRC Action-Qualifier Continuous Software Force Register Section 14.4.3.4 SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 352: Action-Qualifier Output A Control Register (Aqctla)
Set: force EPWMxA output high. Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 353: Action-Qualifier Output B Control Register (Aqctlb)
Set: force EPWMxB output high. Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low. SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 354: Action-Qualifier Software Force Register (Aqsfrc)
Does nothing (action disabled) Clear (low) Set (high) Toggle (Low → High, High → Low) Note: This action is not qualified by counter direction (CNT_dir) Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 355: Dead-Band Generator Submodule Registers
Dead-Band Generator Control Register Section 14.4.4.1 DBRED Dead-Band Generator Rising Edge Delay Register Section 14.4.4.2 DBFED Dead-Band Generator Falling Edge Delay Register Section 14.4.4.3 SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 356: Dead-Band Generator Control Register (Dbctl)
Dead-band is fully enabled for both rising-edge delay on output EPWMxA and falling-edge delay on output EPWMxB. The input signal for the delay is determined by DBCTL[IN_MODE]. Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 357: Dead-Band Generator Rising Edge Delay Register (Dbred)
Table 14-69. Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions Bits Name Value Description 15-10 Reserved Reserved 0-3FFh Falling Edge Delay Count. 10-bit counter SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 358: Pwm-Chopper Submodule Register
3 × SYSCLKOUT/8 wide 3h-Fh 4 × SYSCLKOUT/8 wide to 16 × SYSCLKOUT/8 wide CHPEN PWM-chopping Enable Disable (bypass) PWM chopping function Enable chopping function Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 359: Trip-Zone Submodule Registers
Disable TZn as a CBC trip source for this ePWM module. Enable TZn as a CBC trip source for this ePWM module. SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 360: Trip-Zone Control Register (Tzctl)
Trip-zone Cycle-by-Cycle Interrupt Enable Disable cycle-by-cycle interrupt generation. Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMxTZINT interrupt. Reserved Reserved Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 361: Trip-Zone Flag Register (Tzflg)
CBC or OST is set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. This bit is cleared by writing the appropriate value to the TZCLR register (Section 14.4.6.5). SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 362: Trip-Zone Clear Register (Tzclr)
Writing of 0 is ignored. Always reads back a 0. Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit. Reserved Reserved Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 363: Event-Trigger Submodule Registers
Enable event: time-base counter equal to CMPB when the timer is incrementing. Enable event: time-base counter equal to CMPB when the timer is decrementing. SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 364: Event-Trigger Prescale Register (Etps)
Generate an interrupt on the first event INTCNT = 01 (first event) Generate interrupt on ETPS[INTCNT] = 1,0 (second event) Generate interrupt on ETPS[INTCNT] = 1,1 (third event) Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 365: Event-Trigger Flag Register (Etflg)
Writing a 0 has no effect. Always reads back a 0. Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated. SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 366: High-Resolution Pwm Submodule Registers
Section TBPHSHR Time-Base Phase High-Resolution Register Section 14.4.8.1 CMPAHR Counter-Compare A High-Resolution Register Section 14.4.8.2 1040h HRCNFG HRPWM Configuration Register Section 14.4.8.3 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 367: Time-Base Phase High-Resolution Register (Tbphshr)
Compare A High-Resolution register bits for MEP step control. A minimum value of 1h is needed to enable HRPWM capabilities. Valid MEP range of operation 1-255h. Reserved Reserved SPRUH90B – March 2013 Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 368: Hrpwm Configuration Register (Hrcnfg)
HRPWM capability is disabled (default on reset) MEP control of rising edge MEP control of falling edge MEP control of both edges Enhanced High-Resolution Pulse-Width Modulator (eHRPWM) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 369: Enhanced Quadrature Encoder Pulse (Eqep) Module
This chapter describes the eQEP..........................Topic Page ....................15.1 Introduction ....................15.2 Architecture ....................15.3 eQEP Registers SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 370: Introduction
166.6 KHz, so by measuring the frequency of either the QEPA or QEPB output, the processor can determine the velocity of the motor. Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 371: Qep Encoder Output Signal For Forward/Reverse Movement
Figure 15-3. Index Pulse Example QEPA QEPB ±0.1T 0.25T QEPI (gated to A and B) ±0.1T 0.5T QEPI (gated to A) ±0.5T QEPI (ungated) SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 372 DSP software switch over to Equation 1 when the motor speed rises above some specified threshold. Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 373: Architecture
Quadrature edge-capture unit for low-speed measurement (QCAP) • Unit time base for speed/frequency measurement (UTIME) • Watchdog timer for detecting stalls (QWDOG) SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 374: Functional Block Diagram Of The Eqep Peripheral
(QDU) EQEPxI EQEPxSIN QPOSSLAT PCSOUT EQEPxSOUT QPOSILAT EQEPxS EQEPxSOE QPOSCNT QEINT QPOSCMP QPOSINIT QFRC QPOSMAX QCLR QPOSCTL Enhanced QEP (eQEP) peripheral Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 375: Quadrature Decoder Unit (Qdu)
QDIR QDECCTL:QBP x1, x2 QDECCTL:QSRC QDECCTL:XCR QDECCTL:QIP EQEPxIIN QDECCTL:IGATE EQEPxSIN QDECCTL:QSP QDECCTL:SPSEL EQEPxIOUT PCSOUT EQEPxSOUT QDECCTL:SPSEL EQEPxIOE QDECCTL:SOEN EQEPxSOE SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 376: Quadrature Decoder Truth Table
QA↑ DOWN Increment QA↓ Decrement QB↓ TOGGLE Increment or Decrement QB↓ QA↓ DOWN Increment QA↑ Decrement QB↑ TOGGLE Increment or Decrement Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 377: Quadrature Decoder State Machine
−1 −1 QCLK QDIR QPOSCNT −1 −1 −1 −1 −1 −1 −1 +1 +1 +1 +1 +1 +1 −1 −1 −1 SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 378: Position Counter And Control Unit (Pccu)
Position Counter Reset on Maximum Position • Position Counter Reset on the first Index Event • Position Counter Reset on Unit Time Out Event (Frequency Measurement) Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 379: Position Counter Reset By Index Pulse For 1000 Line Encoder (Qposmax = 3999 Or F9Fh)
Figure 15-8. Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or F9Fh) QCLK QEPSTS:QDF QPOSCNT F9C Index interrupt/ index event marker QPOSILAT QEPSTS:QDLF SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 380: Position Counter Underflow/Overflow (Qposmax = 4)
(QEPCTL[IEL]=11). Figure 15-9. Position Counter Underflow/Overflow (QPOSMAX = 4) QCLK QDIR QPOSCNT OV/UF QCLK QDIR QPOSCNT OV/UF Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 381 (QEPCTL[IEL] = 11). Figure 15-10 shows the position counter latch using an index event marker. SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 382: Software Index Marker For 1000-Line Encoder (Qepctl[Iel] = 1)
Figure 15-10. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1) QCLK QEPSTS:QDF QPOSCNT Index interrupt/ index event marker QPOSILAT QEPSTS:QDLF Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 383: Strobe Event Latch (Qepctl[Sel] = 1)
The strobe event latch interrupt flag (QFLG[SEL]) is set when the position counter is latched to the QPOSSLAT register. Figure 15-11. Strobe Event Latch (QEPCTL[SEL] = 1) QCLK QEPST:QDF QPOSCNT QIPOSSLAT SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 384: Eqep Position-Compare Unit
(QFLG[PCR]) interrupt after loading. • Load on compare match • Load on position-counter zero event Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 385: Eqep Position-Compare Event Generation Points
Figure 15-14. Figure 15-14. eQEP Position-compare Sync Output Pulse Stretcher QPOSCMP QPOSCNT PCEVNT PCSPW PCSPW PCSPW PCSOUT (active HIGH) SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 386: Eqep Edge Capture Unit
The QCAPCTL register should not be modified dynamically (such as switching CAPCLK prescaling mode from QCLK/4 to QCLK/8). The capture unit must be disabled before changing the prescaler. Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 387: Eqep Edge Capture Unit
Figure 15-16. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010) QCLK UPEVNT X=N x P N - Number of quadrature periods selected using QCAPCTL[UPPS] bits SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 388: Eqep Edge Capture Unit - Timing Details
Unit time (T) and unit period (X) are configured using the QUPRD and QCAPCTL[UPPS] registers. Incremental position output and incremental time output is available in the QPOSLAT and QCPRDLAT registers. Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 389: Eqep Watchdog
(QFLG[WTO]). The time-out value is programmable through the watchdog period register (QWDPRD). Figure 15-18. eQEP Watchdog Timer QWDOG QEPCTL:WDE SYSCLKOUT SYSCLKOUT QWDTMR QCLK RESET WDTOUT QWDPRD QFLG:WTO SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 390: Unit Timer Base
You can force an interrupt event by way of the interrupt force register (QFRC), which is useful for test purposes. Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 391: Eqep Registers
Capture Timer Latch Register Section 15.3.23 QCPRDLAT eQEP Capture Period Latch Register Section 15.3.24 REVID eQEP Revision ID Register Section 15.3.25 SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 392: Eqep Position Counter Register (Qposcnt)
Table 15-5. eQEP Maximum Position Count Register (QPOSMAX) Field Descriptions Bits Name Value Description 31-0 QPOSMAX 0-FFFF FFFFh This register contains the maximum position counter value. Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 393: Eqep Position-Compare Register (Qposcmp)
31-0 QPOSSLAT 0-FFFF FFFFh The position-counter value is latched into this register on strobe event as defined by the QEPCTL[SEL] bits. SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 394: Eqep Position Counter Latch Register (Qposlat)
This register contains the period count for unit timer to generate periodic unit time events to latch the eQEP position information at periodic interval and optionally to generate interrupt. Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 395: Eqep Watchdog Timer Register (Qwdtmr)
This register contains the time-out count for the eQEP peripheral watch dog timer. When the watchdog timer value matches the watchdog period value, a watchdog timeout interrupt is generated. SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 396: Qep Decoder Control Register (Qdecctl)
QEPI input polarity No effect Negates QEPI input QEPS input polarity No effect Negates QEPS input Reserved Always write as 0 Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 397: Eqep Control Register (Qepctl)
Initializes the position counter on the falling edge of QEPI signal (QPOSCNT = QPOSINIT) Software initialization of position counter Do nothing (action disabled) Initialize position counter, this bit is cleared automatically SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 398 Disable eQEP unit timer Enable unit timer eQEP watchdog enable Disable the eQEP watchdog timer Enable the eQEP watchdog timer Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 399: Eqep Capture Control Register (Qcapctl)
UPEVNT = QCLK/32 UPEVNT = QCLK/64 UPEVNT = QCLK/128 UPEVNT = QCLK/256 UPEVNT = QCLK/512 UPEVNT = QCLK/1024 UPEVNT = QCLK/2048 Ch-Fh Reserved SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 400: Eqep Position-Compare Control Register (Qposctl)
1 × 4 × SYSCLKOUT cycles 2 × 4 × SYSCLKOUT cycles 2h-FFFh 3 × 4 × SYSCLKOUT cycles to 4096 × 4 × SYSCLKOUT cycles Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 401: Eqep Interrupt Enable Register (Qeint)
Quadrature phase error interrupt enable Interrupt is disabled Interrupt is enabled Position counter error interrupt enable Interrupt is disabled Interrupt is enabled Reserved Reserved SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 402: Eqep Interrupt Flag Register (Qflg)
No interrupt generated Set on simultaneous transition of QEPA and QEPB Position counter error interrupt flag No interrupt generated Position counter error Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 403: Eqep Interrupt Clear Register (Qclr)
Clear watchdog timeout interrupt flag No effect Clears the interrupt flag Clear quadrature direction change interrupt flag No effect Clears the interrupt flag SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 404 No effect Clears the interrupt flag and enables further interrupts to be generated if an event flags is set to 1. Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 405: Eqep Interrupt Force Register (Qfrc)
Force quadrature phase error interrupt No effect Force the interrupt Force position counter error interrupt No effect Force the interrupt Reserved Always write as 0 SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 406: Eqep Status Register (Qepsts)
Position counter error flag. This bit is not sticky and it is updated for every index event. No error occurred during the last index transition. Position counter error Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 407: Eqep Capture Timer Register (Qctmr)
0-FFFFh The eQEP capture timer value can be latched into this register on two events viz., unit timeout event, reading the eQEP position counter. SPRUH90B – March 2013 Enhanced Quadrature Encoder Pulse (eQEP) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 408: Eqep Capture Period Latch Register (Qcprdlat)
LEGEND: R = Read only; -n = value after reset Table 15-27. eQEP Revision ID Register (REVID) Field Descriptions Bits Name Value Description 31-0 44D3 1103h eQEP revision ID Enhanced Quadrature Encoder Pulse (eQEP) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 409: Enhanced Direct Memory Access (Edma3) Controller
16.1 Introduction ....................16.2 Architecture ................... 16.3 Transfer Examples ......................16.4 Registers ........................ 16.5 Tips ..................16.6 Setting Up a Transfer SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 410: Introduction
– Error and status recording to facilitate debug – Missed event detection • 128 parameter RAM (PaRAM) entries • 4 shadow regions Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 411 16-, 32-, or 64-bytes burst size. See the Chip Configuration 0 Register (CFGCHIP0) in the System Configuration (SYSCFG) Module chapter for details to change the default burst size value. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 412: Functional Block Diagram
Transfer controllers are the transfer engine for the EDMA3. Performs the controller(s) read/writes as dictated by the transfer requests submitted by the EDMA3CC. (EDMA3TC) Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 413 QDMA channel n mapping register (QCHMAPn) and can point to any PaRAM set entry. TR synchronization See Trigger event. (sync) event SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 414: Architecture
DMA channels being higher priority than the QDMA channels. Among the two groups of channels, the lowest-numbered channel is the highest priority. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 415: Edma3 Channel Controller (Edma3Cc) Block Diagram
Additionally, the EDMA3CC also has an error detection logic, which causes error interrupt generation on various error conditions (like missed events, exceeding event queue thresholds, etc.). For more details on error interrupts, see Section 16.2.9.4. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 416: Edma3 Transfer Controller (Edma3Tc) Block Diagram
For details on command fragmentation and optimization, see Section 16.2.11.1.2. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 417: Types Of Edma3 Transfers
Array 2 Array BCNT CCNT frames in Block/3rd dimmension Frame CCNT Array 1 Array 2 Array BCNT BCNT arrays in Frame/2nd dimmension SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 418: A-Synchronized Transfers (Acnt = N, Bcnt = 4, Ccnt = 3)
Array 2 Array 3 (SRC|DST) CIDX (SRC|DST) (SRC|DST) (SRC|DST) BIDX BIDX BIDX Frame 2 Array 0 Array 1 Array 2 Array 3 Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 419: Ab-Synchronized Transfers (Acnt = N, Bcnt = 4, Ccnt = 3)
Array 2 Array 3 NOTE: ABC-synchronized transfers are not directly supported. But can be logically achieved by chaining between multiple AB-synchronized transfers. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 420: Parameter Ram (Param)
Parameter set n−1 Parameter set n Note: n is the number of PaRAM sets supported in the EDMA3CC for a specific device. 420 Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 421: Edma3 Channel Parameter Description
32-bit accesses on the parameter RAM for best code compatibility. For example, switching the endianness of the processor swaps addresses of the 16-bit fields, but 32-bit accesses avoid the issue entirely. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 422 For AB-synchronized transfers, the EDMA3CC submits the BCNT in the TR and the EDMA3TC decrements BCNT appropriately. For AB-synchronized transfers, BCNTRLD is not used. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 423 You should make sure to program the LINK field correctly, so that link update is requested from a PaRAM address that falls in the range of the available PaRAM addresses on the device. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 424: Dummy And Null Transfer Request
A link update occurs when the PaRAM set is exhausted, as described in Section 16.2.3.7. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 425: Parameter Updates In Edma3Cc (For Non-Null, Non-Dummy Param Set)
You should ensure that no transfer is allowed to cross internal port boundaries between peripherals. A single TR must target a single source/destination slave endpoint. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 426 PaRAM entry is defined as a trigger word, EDMA3CC logic assures that all 8 PaRAM words are updated before the new QDMA event can trigger the transfer for that PaRAM entry. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 427 ACNT = 2 (2 bytes) and BCNT = 256. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 428: Linked Transfer Example
01C0 4040h Parameter set 2 01C0 4060h Parameter set 3 Link=FFFFh 01C0 4FC0h Parameter set 126 1CA0 4FE0h Parameter set 127 Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 429: Link-To-Self Transfer Example
SRCBIDX X BCNTRLD X Link=4FE0h DSTCIDX X SRCCIDX X 01C0 4FC0h Parameter set 126 1CA0 4FE0h Parameter set 127 Rsvd CCNT X SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 430: Initiating A Dma Transfer
For the synchronization events associated with each of the programmable DMA channels, see your device-specific data manual to determine the event to channel mapping. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 431 NOTE: Chained event registers, event registers, and event set registers operate independently. An event (En) can be triggered by any of the trigger sources (event-triggered, manually- triggered, or chain-triggered). SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 432 PaRAM set mapped to the QDMA channel will automatically be recognized as a valid QDMA event and initiate another set of transfers as specified by the linked set. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 433: Completion Of A Dma Transfer
There are three ways the EDMA3CC gets updated/informed about a transfer completion: normal completion, early completion, and dummy/null completion. This applies to both chained events and completion interrupt generation. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 434: Event, Channel, And Param Mapping
(unused), that channel can be used for manually-triggered or chained-triggered transfers, for linking/reloading, or as a QDMA channel. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 435: Edma3 Dma Channel To Param Mapping
Reload/QDMA PaRAM Set 33 Reload/QDMA PaRAM Set n - 2 Reload/QDMA PaRAM Set n - 1 Reload/QDMA PaRAM Set n Reload/QDMA SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 436: Qdma Channel To Param Mapping
Parameter set n−1 Parameter set n Note: n is the number of PaRAM sets supported in the EDMA3CC for a specific device. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 437: Edma3 Channel Controller Regions
Table 16-6. Shadow Region Registers DRAEm QRAEm QEER QEECR QEESR EECR EESR SECR IECR IESR Register not affected by DRAE IEVAL SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 438: Shadow Region Registers
DRAE/QRAE registers. If exclusive access to any given channel/TCC code is required for a region, then only that region's DRAE/QRAE should have the associated bit set. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 439: Chaining Edma3 Channels
20 (All TRs) 5 (All TRs) 16.2.9 EDMA3 Interrupts The EDMA3 interrupts are divided into 2 categories: • Transfer completion interrupts SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 440: Transfer Complete Code (Tcc) To Edma3Cc Interrupt Mapping
00 0001b IPR1 00 0010b IPR2 00 0011b IPR3 00 0100b IPR4 … … … … 01 1110b IPR30 01 1111b IPR31 Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 441: Number Of Interrupts
EDMA3CC_INT1: (IPR.E0 & IER.E0 & DRAE1.E0) | (IPR.E1 & IER.E1 & DRAE1.E1) | …| (IPR.En & IER.En & DRAE1.En) where n is the number of shadow regions supported in the EDMA3CC for a specific device. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 442: Interrupt Diagram
Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 443 If this happens, a new interrupt is recorded in the device interrupt controller and a new interrupt is generated as soon as the application exits the interrupt service routine. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 444 NOTE: While using IEVAL for shadow region completion interrupts, you should make sure that the IEVAL operated upon is from that particular shadow region memory map. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 445: Error Interrupt Operation
QEMR CCERR EEVAL.EVAL Eval/ pulse EDMA3_CC0_ERRINT Note: n is the number of queues supported in the EDMA3CC for a specific device. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 446: Event Queue(S)
EDMA3TC. In this case, the event is not logged in the event queue status registers. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 447 (CCERR) and the THRXCD bit in QSTATn, where n stands for the event queue number. Any bits that are set in CCERR also generate an EDMA3CC error interrupt. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 448: Edma3 Transfer Controller (Edma3Tc)
DBS value, then the EDMA3TC breaks the ACNT array into DBS-sized commands to the source/destination addresses. Each BCNT number of arrays are then serviced in succession. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 449 TR0), the transfer controller issues that the write commands are issued in order (that is, write commands for TR0 will be issued before write commands for TR1). SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 450 FIFO register entry 3 and the second pending TR is read from the destination FIFO register entry 0. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 451: Event Dataflow
10. This continues until the TR completes and on receiving the acknowledgement signal from the destination slave end point, the EDMA3TCn then signals completion status to the EDMA3CC. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 452: Edma3 Prioritization
QDMA event Completion register interface (QER) QDMA trigger Completion detection From EDMA3TC(s) Error Completion detection interrupt EDMA3 channel controller EDMA3CC_ERRINT EDMA3CC_INT[1:0] Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 453 EDMA3CC memory-map. However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the System Configuration Module. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 454: Edma3Cc And Edma3Tc Performance And System Considerations
TC will end up issuing several ACNT byte (4 byte) size commands to complete the transfers, which will result in inefficient usage of the read/write buses. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 455: Edma3 Operating Frequency (Clock Control)
DMA channel associated with the peripheral (clearing the EER bit for the channel), then disable the EDMA3CC, and finally disable the EDMA3TC(s). SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 456: Emulation Considerations
Figure 16-15. Block Move Example 4000 0000h 1180 0000h 245 246 247 248 245 246 247 249 250 251 252 253 254 253 254 255 Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 457: Block Move Example Param Configuration
(b) Channel Options Parameter (OPT) Content 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0000 0000 TCCMOD FWID Reserved STATIC SYNCDIM SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 458: Subframe Extraction Example
(b) Channel Options Parameter (OPT) Content 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0000 0000 TCCMOD FWID Reserved STATIC SYNCDIM Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 459: Data Sorting Example
B_1022 B_1023 B_1024 C_1022 C_1023 C_1024 D_1022 D_1023 D_1024 A_1022 B_1022 C_1022 D_1022 A_1023 B_1023 C_1023 D_1023 A_1024 B_1024 C_1024 D_1024 SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 460: Data Sorting Example Param Configuration
(b) Channel Options Parameter (OPT) Content 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0000 0000 TCCMOD FWID Reserved STATIC SYNCDIM Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 461: Peripheral Servicing Example
Based on the premise that serial data is typically a high priority, the DMA channel should be programmed to be on queue 0. Figure 16-21. Servicing Incoming McBSP Data Example 1180 0000h REVT 01D0 0000h SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 462: Servicing Incoming Mcbsp Data Example Param
(b) Channel Options Parameter (OPT) Content 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0000 0000 TCCMOD FWID Reserved STATIC SYNCDIM Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 463: Servicing Peripheral Burst Example
(b) Channel Options Parameter (OPT) Content 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0000 0000 TCCMOD FWID Reserved STATIC SYNCDIM SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 464: Servicing Continuous Mcbsp Data Example
A1o A2o A3o A4o A5o A1..B1..A2..B2..A3..B3..A4..B4..A5..B5 01D0 0004h A9i A10i A11i A12i A13i 1180 1080h B7o B8o B9o B10o B11o B12o B13o Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 465: Servicing Continuous Mcbsp Data Example Param
(d) Channel Options Parameter (OPT) Content for Transmit Channel (PaRAM Set 2) 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0001 0000 TCCMOD FWID Reserved STATIC SYNCDIM SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 466: Servicing Continuous Mcbsp Data Example Reload Param
(d) Channel Options Parameter (OPT) Content for Transmit Channel (PaRAM Set 65) 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0001 0000 TCCMOD FWID Reserved STATIC SYNCDIM Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 467 The only differences are the link address provided and the address of the data buffer. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 468: Ping-Pong Buffering For Mcbsp Data Example
A10i A11i A12i A13i 1180 1080h 1180 1880h B9o B10o B11o B12o B13o B9o B10o B11o B12o B13o A1..B1..A2..B2..A3..B3..A4..B4..A5..B5 01D0 0004h Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 469: Ping-Pong Buffering For Mcbsp Example Param
(d) Channel Options Parameter (OPT) Content for Channel 2 0000 PRIV Reserved PRIVID ITCCHEN TCCHEN ITCINTEN TCINTEN Reserved 0010 0000 TCCMOD FWID Reserved STATIC SYNCDIM SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 470: Ping-Pong Buffering For Mcbsp Example Pong Param
Link Address (LINK) 0000h 0000h Destination CCNT Index (DSTCIDX) Source CCNT Index (SRCCIDX) 0000h 0001h Reserved Count for 3rd Dimension (CCNT) Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 471 Figure 16-34 shows the EDMA3 setup and illustration of the broken up smaller packet transfers. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 472: Intermediate Transfer Completion Chaining Example
16 KBytes data transfer BCNT = 1 CCNT = 1 1D transfer of 16 KByte elements OPT.ITCINTEN = 0 OPT.TCC = Don’t care Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 473: Registers
Section 16.4.1.5 LINK_BCNTRLD Link Address/B Count Reload Section 16.4.1.6 SRC_DST_CIDX Source C Index/Destination C Index Section 16.4.1.7 CCNT C Count Section 16.4.1.8 SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 474: Channel Options Parameter (Opt)
CPU, the corresponding IER[TCC] bit must be set to 1. Reserved Reserved. Always write 0 to this bit. Reserved Reserved Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 475 If the constant addressing mode is not supported, the similar logical transfer can be achieved using the increment (INCR) mode (SAM/DAM = 0) by appropriately programming the count and indices values. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 476: Channel Source Address Parameter (Src)
0-FFFFh A count for 1st Dimension. Unsigned value specifying the number of contiguous bytes within an array (first dimension of the transfer). Valid values range from 1 to 65 535. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 477: Channel Destination Address Parameter (Dst)
Source B index. Signed value specifying the byte address offset between source arrays within a frame (2nd dimension). Valid values range from –32 768 and 32 767. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 478: Link Address/B Count Reload Parameter (Link_Bcntrld)
PaRAM set. The 5 LSBs of the LINK field should be cleared to 0. A value of FFFFh specifies a null link. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 479: Source C Index/Destination C Index Parameter (Src_Dst_Cidx)
C counter. Unsigned value specifying the number of frames in a block, where a frame is BCNT arrays of ACNT bytes. Valid values range from 1 to 65 535. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 480: Edma3 Channel Controller (Edma3Cc) Registers
However for this device, the priority control for the transfer controllers is controlled by the chip-level registers in the System Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority. 480 Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 481 QDMA Event Enable Set Register — 2090h QSER QDMA Secondary Event Register — 2094h QSECR QDMA Secondary Event Clear Register — SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 482 2290h QSER QDMA Secondary Event Register — 2294h QSECR QDMA Secondary Event Clear Register — 4000h-4FFFh — Parameter RAM (PaRAM) — Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 483: Revision Id Register (Revid)
Reserved NUM_DMACH R-4h R-4h LEGEND: R = Read only; -n = value after reset; -x = value is indeterminate after reset SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 484: Edma3Cc Configuration Register (Cccfg) Field Descriptions
Reserved 8 QDMA channels 5h-7h Reserved Reserved Reserved NUM_DMACH 0-7h Number of DMA channels. 0-3h Reserved 32 DMA channels 5h-7h Reserved Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 485: Qdma Channel N Mapping Register (Qchmapn)
Points to the specific PaRAM entry or the trigger word in the PaRAM set pointed to by PAENTRY. A write to the trigger word results in a QDMA event being recognized. Reserved Reserved SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 486: Dma Channel Queue Number Register N (Dmaqnumn)
Event n is queued on Q1. 2h-7h Reserved Table 16-25. Bits in DMAQNUMn DMAQNUMn En bit 8-10 12-14 16-18 20-22 24-26 28-30 Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 487: Qdma Channel Queue Number Register (Qdmaqnum)
System Configuration Module. You should use the chip-level registers and not QUEPRI to configure the TC priority. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 488: Event Missed Register (Emr)
Channel 0-31 event missed. En is cleared by writing a 1 to the corresponding bit in the event missed clear register (EMCR). No missed event. Missed event occurred. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 489: Event Missed Clear Register (Emcr)
Event missed 0-31 clear. All error bits must be cleared before additional error interrupts will be asserted by the EDMA3CC. No effect. Corresponding missed event bit in the event missed register (EMR) is cleared (En = 0). SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 490: Qdma Event Missed Register (Qemr)
Channel 0-7 QDMA event missed. En is cleared by writing a 1 to the corresponding bit in the QDMA event missed clear register (QEMCR). No missed event. Missed event occurred. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 491: Qdma Event Missed Clear Register (Qemcr)
EDMA3CC. No effect. Corresponding missed event bit in the QDMA event missed register (QEMR) is cleared (En = 0). SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 492: Edma3Cc Error Register (Ccerr)
Queue threshold error for queue 0. QTHRXCD0 is cleared by writing a 1 to the corresponding bit in the EDMA3CC error clear register (CCERRCLR). Watermark/threshold has not been exceeded. Watermark/threshold has been exceeded. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 493: Edma3Cc Error Clear Register (Ccerrclr)
Clears the QTHRXCD0 bit in the EDMA3CC error register (CCERR) and the WM and THRXCD bits in the queue status register 0 (QSTAT0). SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 494: Error Evaluate Register (Eeval)
EDMA3CC error interrupt will be pulsed if any errors have not been cleared in any of the error registers (EMR, QEMR, or CCERR). Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 495: Dma Region Access Enable Register For Region M (Draem)
Enabled interrupt bits for bit n contribute to the generation of a transfer completion interrupt for shadow region m. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 496: Qdma Region Access Enable For Region M (Qraem)
Accesses via region m address space to bit n in any QDMA channel register are allowed. Reads return the value from bit n and writes modify the state of bit n. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 497: Event Queue Entry Registers (Qxey)
Event entry y in queue x. Event number: 0-7h QDMA channel number (0 to 7) 0-1Fh DMA channel/event number (0 to 31) SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 498: Queue N Status Register (Qstatn)
Start pointer. The offset to the head entry of queue n, in units of entries. Always enabled. Legal values are 0 (0th entry) to Fh (15th entry). Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 499: Queue Watermark Threshold A Register (Qwmthra)
0 at an instant in time (visible via the NUMVAL bit in QSTAT0) equals or exceeds the value specified by Q0. 0-10h The default is 16 (maximum allowed). Disables the threshold errors. 12h-1Fh Reserved SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 500: Edma3Cc Status Register (Ccstat)
Either the write status request is active or additional write status responses are pending in the write status fifo. TRACTV Transfer request active. Transfer request processing/submission logic is inactive. Transfer request processing/submission logic is active. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 501 No enabled DMA events are active within the EDMA3CC. At least one enabled DMA event (ER and EER, ESR, CER) is active within the EDMA3CC. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 502: Event Register (Er)
EDMA3CC event is not asserted. EDMA3CC event is asserted. Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 503: Event Clear Register (Ecr)
Event clear for event 0-31. Any of the event bits in ECR is set to 1 to clear the event (En) in the event register (ER). A write of 0 has no effect. No effect. EDMA3CC event is cleared in the event register (ER). SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 504: Event Set Register (Esr)
Event set for event 0-31. No effect. Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 505: Chained Event Register (Cer)
Chained event for event 0-31. No effect. Corresponding DMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 506: Event Enable Register (Eer)
Event is not enabled. An external event latched in the event register (ER) is not evaluated by the EDMA3CC. Event is enabled. An external event latched in the event register (ER) is evaluated by the EDMA3CC. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 507: Event Enable Clear Register (Eecr)
Event enable set for events 0-31. No effect. Event is enabled. Corresponding bit in the event enable register (EER) is set (En = 1). SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 508: Secondary Event Register (Ser)
Description 31-0 Secondary event clear register No effect. Corresponding bit in the secondary event register (SER) is cleared (En = 0). Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 509: Interrupt Enable Register (Ier) Field Descriptions
Table 16-49. Interrupt Enable Register (IER) Field Descriptions Field Value Description 31-0 Interrupt enable for channels 0-31. Interrupt is not enabled. Interrupt is enabled. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 510: Interrupt Enable Clear Register (Iecr)
Interrupt enable set for channels 0-31. No effect. Corresponding bit in the interrupt enable register (IER) is set (In = 1). Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 511: Interrupt Pending Register (Ipr)
Interrupt transfer completion code is not detected or was cleared. Interrupt transfer completion code is detected (In = 1, n = EDMA3TC[5:0]). SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 512: Interrupt Clear Register (Icr)
Interrupt clear register for TCC = 0-31. No effect. Corresponding bit in the interrupt pending register (IPR) is cleared (In = 0). Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 513: Interrupt Evaluate Register (Ieval)
For example, writing to the EVAL bit in IEVAL0 pulses the region 0 completion interrupt, but writing to the EVAL bit in IEVAL1 pulses the region 1 completion interrupt. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 514: Qdma Event Register (Qer)
QDMA event for channels 0-7. No effect. Corresponding QDMA event is prioritized versus other pending DMA/QDMA events for submission to the EDMA3TC. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 515: Qdma Event Enable Register (Qeer)
(QER). QDMA channel n is enabled. QDMA events will be recognized and will get latched in the QDMA event register (QER). SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 516: Qdma Event Enable Clear Register (Qeecr)
QDMA event enable set for channels 0-7. No effect. QDMA event is enabled. Corresponding bit in the QDMA event enable register (QEER) is set (En = 1). Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 517: Qdma Secondary Event Register (Qser)
QDMA event is not currently stored in the event queue. QDMA event is currently stored in event queue. EDMA3CC will not prioritize additional events. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 518: Qdma Secondary Event Clear Register (Qsecr)
No effect. Corresponding bit in the QDMA secondary event register (QSER) and the QDMA event register (QER) is cleared (En = 0). Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 519: Edma3 Transfer Controller (Edma3Tc) Registers
Section 16.4.3.6.13 3C4h DFSRC3 Destination FIFO Source Address Register 3 Section 16.4.3.6.14 3C8h DFCNT3 Destination FIFO Count Register 3 Section 16.4.3.6.15 SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 520: Revision Id Register (Revid)
Table 16-62. Revision ID Register (REVID) Field Descriptions Field Value Description 31-0 Peripheral identifier. 4000 3B00h Uniquely identifies the EDMA3TC and the specific revision of the EDMA3TC. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 521: Edma3Tc Configuration Register (Tccfg)
Reserved Reserved Reserved FIFOSIZE 0-7h FIFO size. 32-byte FIFO 64-byte FIFO 128-byte FIFO (for EDMA3TC0 and EDMA3TC1) 256-byte FIFO 4h-7h Reserved SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 522: Edma3Tc Channel Status Register (Tcstat)
Source active set is busy servicing a transfer request. PROGBUSY Program register set busy. Program set idle and is available for programming by the EDMA3CC. Program set busy. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 523: Error Status Register (Errstat)
EDMA3TC has detected an error at source or destination address. Error information can be read from the error details register (ERRDET). SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 524: Error Enable Register (Erren)
Interrupt enable for bus error (BUSERR). BUSERR is disabled. BUSERR is enabled and contributes to the state of EDMA3TC error interrupt generation. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 525: Error Clear Register (Errclr)
Interrupt clear for the bus error (BUSERR) bit in the error status register (ERRSTAT). No effect. Clears the BUSERR bit in the error status register (ERRSTAT) and clears the error details register (ERRDET). SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 526: Error Details Register (Errdet)
Read exclusive operation error Reserved Write addressing error Write privilege error Write timeout error Write data error Dh-Eh Reserved Write exclusive operation error Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 527: Error Interrupt Command Register (Errcmd)
Error evaluate. No effect. EDMA3TC error line is pulsed if any of the error status register (ERRSTAT) bits are set to 1. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 528: Read Command Rate Register (Rdrate)
4 EDMA3TC cycles between reads. 8 EDMA3TC cycles between reads. 16 EDMA3TC cycles between reads. 32 EDMA3TC cycles between reads. 5h-7h Reserved Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 529: Source Active Options Register (Saopt)
Transfer priority. Reflects the values programmed in the queue priority register (QUEPRI) in the EDMA3CC. Priority 0 - Highest priority 1h-6h Priority 1 to priority 6 Priority 7 - Lowest priority Reserved Reserved SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 530: Source Active Source Address Register (Sasrc)
Read command appropriately. Represents the amount of data remaining to be Read. It should be 0 when transfer request (TR) is complete. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 531: Source Active Destination Address Register (Sadst)
15-0 SRCBIDX 0-FFFFh B-Index offset between source arrays. Represents the offset in bytes between the starting address of each source array. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 532: Source Active Memory Protection Proxy Register (Sampprxy)
PRIVID of the host that set up the DMA transaction. For any other master that sets up the PaRAM entry. If DSP sets up the PaRAM entry. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 533: Source Active Count Reload Register (Sacntrld)
Table 16-78. Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions Field Value Description 31-0 SADDRBREF 0-FFFF FFFFh Source address B-reference. Represents the starting address for the array currently being Read. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 534: Source Active Destination Address B-Reference Register (Sadstbref)
A-count reload value. Represents the originally programmed value of ACNT. The reload value is used to reinitialize ACNT after each array is serviced. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 535: Destination Fifo Set Source Address B-Reference Register (Dfsrcbref)
0-FFFF FFFFh Destination address reference for the destination FIFO register set. Represents the starting address for the array currently being written. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 536: Destination Fifo Options Register N (Dfoptn)
Increment (INCR) mode. Source addressing within an array increments. Constant addressing (CONST) mode. Source addressing within an array wraps around upon reaching FIFO width. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 537: Destination Fifo Source Address Register N (Dfsrcn)
0-FFFFh A-dimension count. Number of bytes to be transferred in first dimension count/count remaining for destination register set. Represents the amount of data remaining to be written. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 538: Destination Fifo Destination Address Register N (Dfdstn)
B-Index offset between source arrays. Represents the offset in bytes between the starting address of each source array. Always Read as 0. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 539: Destination Fifo Memory Protection Proxy Register N (Dfmpprxyn)
PRIVID of the host that set up the DMA transaction. For any other master that sets up the PaRAM entry If DSP sets up the PaRAM entry SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 540: Tips
31), make sure that DRAE.E31 is also set for a shadow region completion interrupt because the interrupt pending register bit set will be IPR.I31. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 541: Miscellaneous Programming/Debug Tips
EDMA3CC and EDMA3TC. The EDMA3CC status register (CCSTAT) and the EDMA3TC channel status register (TCSTAT) should be used. SPRUH90B – March 2013 Enhanced Direct Memory Access (EDMA3) Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 542: Setting Up A Transfer
IPR. Again, the set bits in IPR must be manually cleared by writing to ICR before the next set of transfers is performed for the same transfer completion code values. Enhanced Direct Memory Access (EDMA3) Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 543: Spruh90B - March 2013
(PHY) device Management Data Input/Output (MDIO) module integrated in the device..........................Topic Page ....................17.1 Introduction ....................17.2 Architecture ......................17.3 Registers SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 544: Introduction
Programmable interrupt logic permits the software driver to restrict the generation of back-to-back interrupts, which allows more work to be performed in a single call to the interrupt service routine. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 545: Functional Block Diagram
EMAC Sub System Control Module 8K CPPI DMA Bus Master Interrupt Interrupts Combiner Register Bus EMAC MDIO Interrupts Interrupts EMAC MDIO Module Module MII/RMII Bus MDIO Bus SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 546: Industry Standard(S) Compliance Statement
(also known as a switch) with a dedicated LAN connecting each bridge port to a single device. Full-duplex operation constitutes a proper subset of the MAC functionality required for half-duplex operation. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 547: Architecture
The transmit and receive clock sources are provided by the external PHY to the MII_TXCLK and MII_RXCLK pins or to the RMII reference clock pin. Data is transmitted and received with respect to the reference clocks of the interface pins. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 548: Memory Map
Figure 17-2. Ethernet Configuration—MII Connections MII_TXCLK MII_TXD[3−0] 2.5 MHz MII_TXEN 25 MHz MII_COL MII_CRS Physical System layer MII_RXCLK Transformer core device MII_RXD[3−0] (PHY) MII_RXDV MII_RXER RJ−45 MDIO_CLK MDIO_D EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 549: Emac And Mdio Signals For Mii Interface
PHY address, register address, and data bit cycles. The MDIO_D pin acts as an output for all but the data bit cycles at which time it is an input for read operations. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 550: Ethernet Configuration-Rmii Connections
PHY address, register address, and data bit cycles. The MDIO_D pin acts as an output for all but the data bit cycles at which time it is an input for read operations. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 551: Ethernet Protocol Overview
60 to 1514 bytes of the packet data. Note that this 4-byte field may or may not be included as part of the packet data, depending on how the EMAC is configured. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 552: Programming Interface
17-6. Figure 17-5. Basic Descriptor Format Bit Fields Word Offset 16 15 Next Descriptor Pointer Buffer Pointer Buffer Offset Buffer Length Flags Packet Length 552 EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 553: Typical Descriptor Linked List
502 bytes −−− −−− pNext pBuffer Packet B Fragment 3 500 bytes −−− pNext (NULL) pBuffer Packet C 1514 1514 bytes SOP | EOP 1514 SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 554 HDP that started the process. This process applies when adding packets to a transmit list, and empty buffers to a receive list. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 555 17-7) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 17-1 shows the transmit buffer descriptor described by a C structure. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 556: Transmit Buffer Descriptor Format
Uint32 PktFlgLen; /* Packet Flags(MSW) and Length(LSW) */ } EMAC_Desc; /* Packet Flags */ #define EMAC_DSC_FLAG_SOP 0x80000000u #define EMAC_DSC_FLAG_EOP 0x40000000u #define EMAC_DSC_FLAG_OWNER 0x20000000u #define EMAC_DSC_FLAG_EOQ 0x10000000u #define EMAC_DSC_FLAG_TDOWNCMPLT 0x08000000u #define EMAC_DSC_FLAG_PASSCRC 0x04000000u EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 557 EOP flag. This bit is set by the software application and is not altered by the EMAC. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 558 CRC bytes, as they are part of the valid packet data. Note that this flag is valid on SOP descriptors only. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 559: Receive Buffer Descriptor Format
Word 2 16 15 Buffer Offset Buffer Length Word 3 OWNER TDOWNCMPLT PASSCRC JABBER OVERSIZE FRAGMENT UNDERSIZED CONTROL OVERRUN CODEERROR ALIGNERROR CRCERROR NOMATCH Packet Length SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 560 The range of legal values for the BUFFEROFFSET register is 0 to (Buffer Length – 1) for the smallest value of buffer length for all descriptors in the list. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 561 This would happen under device driver reset or shutdown conditions. The EMAC sets this bit in the descriptor of the first free buffer when the tear down occurs. No additional queue processing is performed. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 562 EMAC’s address match criteria and was not discarded because the RXCAFEN bit was set in the RXMBPENABLE. Although the packet is a valid Ethernet data packet, it was only received because the EMAC is in promiscuous mode. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 563: Emac Control Module
To arbitrate between the CPU and EMAC buses for access to internal descriptor memory. • To arbitrate between internal EMAC buses for access to system memory. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 564: Mdio Module
• MDIO clock generator • Global PHY detection and link state monitoring • Active PHY monitoring • PHY register user access EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 565: Mdio Module Block Diagram
The user access registers USERACCESSn allows the software to submit the access requests for the PHY connected to the device. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 566 USERACCESSn before initiating a new transaction, to ensure that the previous transaction has completed. The application software can use the ACK bit in USERACCESSn to determine the status of a read transaction. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 567 (USERINTMASKSET), then the bit is also set in the MDIO user command complete interrupt register (USERINTMASKED) and an interrupt is triggered on the CPU. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 568 MDIO_REGS->USERACCESS0 = CSL_FMK(MDIO_USERACCESS0_GO,1u) CSL_FMK(MDIO_USERACCESS0_WRITE,1) CSL_FMK(MDIO_USERACCESS0_REGADR,regadr) CSL_FMK(MDIO_USERACCESS0_PHYADR,phyadr) CSL_FMK(MDIO_USERACCESS0_DATA, data) #define PHYREG_wait() while( CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) ) #define PHYREG_waitResults( results ) { while( CSL_FEXT(MDIO_REGS->USERACCESS0,MDIO_USERACCESS0_GO) ); results = CSL_FEXT(MDIO_REGS->USERACCESS0, MDIO_USERACCESS0_DATA); } EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 569: Emac Module
The receive FIFO consists of three cells of 64-bytes each and associated control logic. The FIFO buffers receive data in preparation for writing into packet buffers in device memory. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 570 MAC transmitter then initiates the packet transmission. The SYNC block transmits the packet over the MII or RMII interfaces in accordance with the 802.3 protocol. Transmit statistics are counted by the statistics block. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 571: Mac Interface
(in the following order): 1. An Interpacket Gap (IPG). 2. A 7-byte preamble (all bytes 55h). 3. A 1-byte start of frame delimiter (5Dh). SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 572 The 16-bit pause time value of FF.FFh. A pause-quantum is 512 bit-times. Pause frames sent to cancel a pause request have a pause time value of 00.00h. • Zero padding to 64-byte data length (EMAC transmits only 64-byte pause frames). EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 573 MII_TXEN is deasserted, then 96 bit times (approximately, but not less) is measured from MII_CRS. 17.2.9.2.5 Back Off The EMAC implements the 802.3 binary exponential back-off algorithm. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 574 The MAC operates at 10 Mbps or 100 Mbps, in half-duplex or full-duplex mode, and with or without pause frame support as configured by the host. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 575: Packet Receive Operation
(MACADDRLO). Since all eight MAC addresses share the upper 40 bits of address, MACADDRHI needs to be written only the first time (for the first channel configured). SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 576 (note that there is no buffer descriptor in this case). Software may read RXnCP to determine if the interrupt was due to a commanded teardown. The read value is FFFF FFFCh, if the interrupt was due to a teardown command. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 577 64 bytes and the value in the receive maximum length register (RXMAXLEN) bytes in length inclusive and contain no code, align, or CRC errors. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 578: Receive Frame Treatment Summary
No undersized/fragment frames are transferred. All address matching frames with and without errors transferred to the address match channel EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 579: Middle Of Frame Overrun Treatment
OVERRUN flag is set in the SOP buffer descriptor. Note that the RXMAXLEN number of bytes cannot be reached for an overrun to occur (it would be truncated). SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 580: Packet Transmit Operation
(TXnCP) to determine if the interrupt was due to a commanded teardown. The read value is FFFF FFFCh, if the interrupt was due to a teardown command. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 581: Receive And Transmit Latency
The short-term average, each 64-byte memory read/write request from the EMAC must be serviced in no more than 5.12 μs. • Any single latency event in request servicing can be no longer than (5.12 × TXCELLTHRESH) μs. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 582: Reset Considerations
MAC status register (MACSTATUS) that gives information about the type of software error that needs to be corrected. For detailed information on error interrupts, see Section 17.2.16.1.4. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 583: Initialization
Also, a PHY can take up to 3 seconds to negotiate a link. Thus, it is advisable to run the MDIO software off a time-based event rather than polling. For more information on PHY control registers, see your PHY device documentation. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 584 TXEN bit in TXCONTROL. Then set the GMIIEN bit in MACCONTROL. 17. Enable the device interrupt in EMAC control module registers CnRXTHRESHEN, CnRXEN, CnTXEN, and CnMISCEN. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 585: Interrupt Support
(RXINTMASKCLEAR). The raw and masked receive interrupt status may be read by reading the receive interrupt status (unmasked) register (RXINTSTATRAW) and the receive interrupt status (masked) register (RXINTSTATMASKED), respectively. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 586 Ownership bit not set in SOP buffer • Zero next buffer descriptor pointer with EOP • Zero buffer pointer • Zero buffer length • Packet length error EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 587 The application software must acknowledge the EMAC control module after receiving MDIO interrupts by writing the appropriate CnMISC key to the EMAC End-Of-Interrupt Vector (MACEOIVECTOR). See Section 17.3.3.12 for the acknowledge key values. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 588 28 interrupt signals: TXPENDn, RXPENDn, RXTHRESHPENDn, STATPEND, HOSTPEND, LINKINT0, and USERINT0. For more details on the interrupt mapping, see the DSP Subsystem chapter . EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 589: Power Management
SOFT and FREE bits affect the operation of the emulation suspend. NOTE: Emulation suspend has not been tested. Table 17-7. Emulation Control SOFT FREE Description Normal operation Emulation suspend Normal operation SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 590: Registers
EMAC Control Module Interrupt Core 2 Receive Threshold Section 17.3.1.8 Interrupt Status Register C2RXSTAT EMAC Control Module Interrupt Core 2 Receive Interrupt Section 17.3.1.9 Status Register 590 EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 591: Emac Control Module Revision Id Register (Revid)
Table 17-9. EMAC Control Module Revision ID Register (REVID) Field Descriptions Field Value Description 31-0 Identifies the EMAC Control Module revision. 4EC8 0100h Current revision of the EMAC Control Module. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 592: Emac Control Module Software Reset Register (Softreset)
Software reset bit for the EMAC Control Module. Clears the interrupt status, control registers, and CPPI Ram on the clock cycle following a write of 1. No software reset. Perform a software reset. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 593: Emac Control Module Interrupt Control Register (Intcontrol)
Reserved 11-0 INTPRESCALE 0-7FFh Number of internal EMAC module reference clock periods within a 4 μs time window (see your device-specific data manual for information). SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 594: Emac Control Module Interrupt Core 0-2 Receive Threshold Interrupt Enable Register (Cnrxthreshen)
RXCH0THRESHEN Enable CnRXTHRESHPULSE interrupt generation for RX Channel 0 CnRXTHRESHPULSE generation is disabled for RX Channel 0. CnRXTHRESHPULSE generation is enabled for RX Channel 0. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 595: Emac Control Module Interrupt Core 0-2 Receive Interrupt Enable Register (Cnrxen)
RXCH0EN Enable CnRXPULSE interrupt generation for RX Channel 0 CnRXPULSE generation is disabled for RX Channel 0. CnRXPULSE generation is enabled for RX Channel 0. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 596: Emac Control Module Interrupt Core 0-2 Transmit Interrupt Enable Register (Cntxen)
TXCH0EN Enable CnTXPULSE interrupt generation for TX Channel 0 CnTXPULSE generation is disabled for TX Channel 0. CnTXPULSE generation is enabled for TX Channel 0. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 597: Emac Control Module Interrupt Core 0-2 Miscellaneous Interrupt Enable Register (Cnmiscen)
Enable CnMISCPULSE interrupt generation when MDIO USERINT0 interrupts (corresponding to USERACCESS0) are generated CnMISCPULSE generation is disabled for MDIO USERINT0. CnMISCPULSE generation is enabled for MDIO USERINT0. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 598: Emac Control Module Interrupt Core 0-2 Receive Threshold Interrupt Status Register (Cnrxthreshstat)
Interrupt status for RX Channel 0 masked by the CnRXTHRESHEN register RX Channel 0 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt. RX Channel 0 satisfies conditions to generate a CnRXTHRESHPULSE interrupt. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 599: Emac Control Module Interrupt Core 0-2 Receive Interrupt Status Register (Cnrxstat)
Interrupt status for RX Channel 0 masked by the CnRXEN register RX Channel 0 does not satisfy conditions to generate a CnRXPULSE interrupt. RX Channel 0 satisfies conditions to generate a CnRXPULSE interrupt. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 600: Emac Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (Cntxstat)
Interrupt status for TX Channel 0 masked by the CnTXEN register TX Channel 0 does not satisfy conditions to generate a CnTXPULSE interrupt. TX Channel 0 satisfies conditions to generate a CnTXPULSE interrupt. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 601: Emac Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register (Cnmiscstat)
Interrupt status for MDIO USERINT0 masked by the CnMISCEN register MDIO USERINT0 does not satisfy conditions to generate a CnMISCPULSE interrupt. MDIO USERINT0 satisfies conditions to generate a CnMISCPULSE interrupt. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 602: Emac Control Module Interrupt Core 0-2 Receive Interrupts Per Millisecond Register (Cnrximax)
= previous_pace_counter + 1; else if(interrupt_count > 0.5*RXIMAX) pace_counter = previous_pace_counter - 1; else if(interrupt_count != 0) pace_counter = previous_pace_counter/2; else pace_counter = 0; previous_pace_counter = pace_counter; EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 603: Emac Control Module Interrupt Core 0-2 Transmit Interrupts Per Millisecond Register (Cntximax)
= previous_pace_counter + 1; else if(interrupt_count > 0.5*TXIMAX) pace_counter = previous_pace_counter - 1; else if(interrupt_count != 0) pace_counter = previous_pace_counter/2; else pace_counter = 0; previous_pace_counter = pace_counter; SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 604: Mdio Registers
Table 17-23. MDIO Revision ID Register (REVID) Field Descriptions Field Value Description 31-0 Identifies the MDIO Module revision. 0007 0104h Current revision of the MDIO Module. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 605: Mdio Control Register (Control)
Clock Divider bits. This field specifies the division ratio between the peripheral clock and the frequency of MDIO_CLK. MDIO_CLK is disabled when CLKDIV is cleared to 0. MDIO_CLK frequency = peripheral clock frequency/(CLKDIV + 1). SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 606: Phy Acknowledge Status Register (Alive)
The PHY indicates it does not have a link or fails to acknowledge the read transaction The PHY with the corresponding address has a link and the PHY acknowledges the read transaction. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 607: Mdio Link Status Change Interrupt (Unmasked) Register (Linkintraw)
No MDIO link change event. An MDIO link change event (change in the LINK register) corresponding to the PHY address in MDIO user PHY select register USERPHYSEL0 SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 608: Mdio Link Status Change Interrupt (Masked) Register (Linkintmasked)
An MDIO link change event (change in the LINK register) corresponding to the PHY address in MDIO user PHY select register USERPHYSEL0 and the LINKINTENB bit in USERPHYSEL0 is set to 1. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 609: Mdio User Command Complete Interrupt (Unmasked) Register (Userintraw)
Writing a 1 will clear the event, writing a 0 has no effect. No MDIO user command complete event. The previously scheduled PHY read or write command using MDIO user access register USERACCESS0 has completed. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 610: Mdio User Command Complete Interrupt (Masked) Register (Userintmasked)
The previously scheduled PHY read or write command using MDIO user access register USERACCESS0 has completed and the corresponding bit in USERINTMASKSET is set to 1. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 611: Mdio User Command Complete Interrupt Mask Set Register (Userintmaskset)
MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is disabled. MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is enabled. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 612: Mdio User Command Complete Interrupt Mask Clear Register (Userintmaskclear)
MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is enabled. MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is disabled. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 613: Mdio User Access Register 0 (Useraccess0)
PHY address bits. This field specifies the PHY to be accessed for this transaction. 15-0 DATA 0-FFFFh User data bits. These bits specify the data value read from or to be written to the specified PHY register. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 614: Mdio User Phy Select Register 0 (Userphysel0)
Link change status interrupts for PHY address specified in PHYADDRMON bits are enabled. Reserved Reserved PHYADRMON 0-1Fh PHY address whose link status is to be monitored. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 615: Mdio User Access Register 1 (Useraccess1)
PHY address bits. This field specifies the PHY to be accessed for this transaction. 15-0 DATA 0-FFFFh User data bits. These bits specify the data value read from or to be written to the specified PHY register. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 616: Mdio User Phy Select Register 1 (Userphysel1)
Link change status interrupts for PHY address specified in PHYADDRMON bits are enabled. Reserved PHY address whose link status is to be monitored. PHYADRMON 0-1Fh PHY address whose link status is to be monitored. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 617: Emac Module Registers
Receive Channel 6 Free Buffer Count Register Section 17.3.3.28 15Ch RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register Section 17.3.3.28 160h MACCONTROL MAC Control Register Section 17.3.3.29 SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 618 Receive Channel 3 Completion Pointer Register Section 17.3.3.49 670h RX4CP Receive Channel 4 Completion Pointer Register Section 17.3.3.49 674h RX5CP Receive Channel 5 Completion Pointer Register Section 17.3.3.49 618 EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 619 Receive FIFO or DMA Start of Frame Overruns Register Section 17.3.3.50.34 288h RXMOFOVERRUNS Receive FIFO or DMA Middle of Frame Overruns Register Section 17.3.3.50.35 28Ch RXDMAOVERRUNS Receive DMA Overruns Register Section 17.3.3.50.36 SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 620: Transmit Revision Id Register (Txrevid)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17-39. Transmit Control Register (TXCONTROL) Field Descriptions Field Value Description 31-1 Reserved Reserved TXEN Transmit enable Transmit is disabled. Transmit is enabled. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 621: Transmit Teardown Register (Txteardown)
Teardown transmit channel 1 Teardown transmit channel 2 Teardown transmit channel 3 Teardown transmit channel 4 Teardown transmit channel 5 Teardown transmit channel 6 Teardown transmit channel 7 SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 622: Receive Revision Id Register (Rxrevid)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 17-42. Receive Control Register (RXCONTROL) Field Descriptions Field Value Description 31-1 Reserved Reserved RXEN Receive enable Receive is disabled. Receive is enabled. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 623: Receive Teardown Register (Rxteardown)
Teardown receive channel 1 Teardown receive channel 2 Teardown receive channel 3 Teardown receive channel 4 Teardown receive channel 5 Teardown receive channel 6 Teardown receive channel 7 SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 624: Transmit Interrupt Status (Unmasked) Register (Txintstatraw)
TX3PEND raw interrupt read (before mask) TX2PEND TX2PEND raw interrupt read (before mask) TX1PEND TX1PEND raw interrupt read (before mask) TX0PEND TX0PEND raw interrupt read (before mask) EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 625: Transmit Interrupt Status (Masked) Register (Txintstatmasked)
TX4PEND TX4PEND masked interrupt read TX3PEND TX3PEND masked interrupt read TX2PEND TX2PEND masked interrupt read TX1PEND TX1PEND masked interrupt read TX0PEND TX0PEND masked interrupt read SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 626: Transmit Interrupt Mask Set Register (Txintmaskset)
Transmit channel 1 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. TX0MASK Transmit channel 0 interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 627: Transmit Interrupt Mask Clear Register (Txintmaskclear)
Transmit channel 1 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. TX0MASK Transmit channel 0 interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 628: Mac Input Vector Register (Macinvector)
Receive channels 0-7 interrupt (RXnTHRESHPEND) pending status. Bit 8 is RX0THRESHPEND. RXPEND 0-FFh Receive channels 0-7 interrupt (RXnPEND) pending status bit. Bit 0 is RX0PEND. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 629: Mac End Of Interrupt Vector Register (Maceoivector)
Acknowledge C1MISC Interrupt (STATPEND, HOSTPEND, MDIO LINKINT0, MDIO USERINT0) Acknowledge C2RXTHRESH Interrupt Acknowledge C2RX Interrupt Acknowledge C2TX Interrupt Acknowledge C2MISC Interrupt (STATPEND, HOSTPEND, MDIO LINKINT0, MDIO USERINT0) Ch-1Fh Reserved SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 630: Receive Interrupt Status (Unmasked) Register (Rxintstatraw)
RX3PEND raw interrupt read (before mask) RX2PEND RX2PEND raw interrupt read (before mask) RX1PEND RX1PEND raw interrupt read (before mask) RX0PEND RX0PEND raw interrupt read (before mask) EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 631: Receive Interrupt Status (Masked) Register (Rxintstatmasked)
RX4PEND RX4PEND masked interrupt read RX3PEND RX3PEND masked interrupt read RX2PEND RX2PEND masked interrupt read RX1PEND RX1PEND masked interrupt read RX0PEND RX0PEND masked interrupt read SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 632: Receive Interrupt Mask Set Register (Rxintmaskset)
Receive channel 1 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. RX0MASK Receive channel 0 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 633: Receive Interrupt Mask Clear Register (Rxintmaskclear)
Receive channel 1 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. RX0MASK Receive channel 0 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 634: Mac Interrupt Status (Unmasked) Register (Macintstatraw)
Table 17-55. MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) Field Descriptions Field Value Description 31-2 Reserved Reserved HOSTPEND Host pending interrupt (HOSTPEND); masked interrupt read. STATPEND Statistics pending interrupt (STATPEND); masked interrupt read. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 635: Mac Interrupt Mask Set Register (Macintmaskset)
Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. STATMASK Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 636: Receive Multicast/Broadcast/Promiscuous Channel Enable Register (Rxmbpenable)
UNDERSIZE bit set in their EOP buffer descriptor. Fragments are short frames that contain CRC / align / code errors and undersized are short frames without errors. Short frames are filtered. Short frames are transferred to memory. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 637 RX multicast enable. Enable received hash matching multicast frames to be copied to the channel selected by RXMULTCH bits. Multicast frames are filtered. Multicast frames are copied to the channel selected by RXMULTCH bits. Reserved Reserved SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 638 Select channel 4 to receive multicast frames Select channel 5 to receive multicast frames Select channel 6 to receive multicast frames Select channel 7 to receive multicast frames EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 639: Receive Unicast Enable Set Register (Rxunicastset)
May be read. RXCH0EN Receive channel 0 unicast enable set bit. Write 1 to set the enable, a write of 0 has no effect. May be read. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 640: Receive Unicast Clear Register (Rxunicastclear)
Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. RXCH0EN Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 641: Receive Maximum Length Register (Rxmaxlen)
15 bytes of the buffer are to be ignored by the EMAC and that valid buffer data starts on byte 16 of the buffer. This value is used for all channels. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 642: Receive Filter Low Priority Frame Threshold Register (Rxfilterlowthresh)
Reserved Reserved RXnFLOWTHRESH 0-FFh Receive flow threshold. These bits contain the threshold value for issuing flow control on incoming frames for channel n (when enabled). EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 643: Receive Channel N Free Buffer Count Register (Rxnfreebuffer)
The host must write this field with the number of buffers that have been freed due to host processing. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 644: Mac Control Register (Maccontrol)
Transmit pacing is enabled. GMIIEN GMII enable bit GMII RX and TX are held in reset. GMII RX and TX are enabled for receive and transmit. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 645 FULLDUPLEX bit. The loopback bit should be changed only when GMIIEN bit is deasserted. Loopback mode is disabled. Loopback mode is enabled. FULLDUPLEX Full duplex mode. Half-duplex mode is enabled. Full-duplex mode is enabled. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 646: Mac Status Register (Macstatus)
The host error occurred on transmit channel 4 The host error occurred on transmit channel 5 The host error occurred on transmit channel 6 The host error occurred on transmit channel 7 EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 647 Any transmission in progress when this bit is asserted will complete. Transmit flow control is inactive. Transmit flow control is active. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 648: Emulation Control Register (Emcontrol)
Not a valid value. Two 64-byte packet cells required to be in the transmit FIFO. Three 64-byte packet cells required to be in the transmit FIFO. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 649: Mac Configuration Register (Macconfig)
If a 1 is read, the reset has not yet occurred. If a 0 is read, then a reset has occurred. A software reset has not occurred. A software reset has occurred. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 650: Mac Source Address Low Bytes Register (Macsrcaddrlo)
MAC source address bits 31-24 (byte 3) 15-8 MACSRCADDR4 0-FFh MAC source address bits 39-32 (byte 4) MACSRCADDR5 0-FFh MAC source address bits 47-40 (byte 5) EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 651: Mac Hash Address Register 1 (Machash1)
Most-significant 32 bits of the hash table corresponding to hash values 32 to 63. If a hash table bit is set, then a group address that hashes to that bit index is accepted. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 652: Back Off Random Number Generator Test Register (Bofftest)
IPG time is not stretched to four times the normal value. Transmit pacing helps reduce capture effects, which improves overall network bandwidth. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 653: Receive Pause Timer Register (Rxpause)
The transmit pause timer is loaded by a received (incoming) pause frame, and then decremented at slot time intervals down to 0, at which time EMAC transmit frames are again enabled. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 654: Mac Address Low Bytes Register (Macaddrlo)
MATCHFILT is cleared to 0. 15-8 MACADDR0 0-FFh MAC address lower 8-0 bits (byte 0) MACADDR1 0-FFh MAC address bits 15-8 (byte 1) EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 655: Mac Address High Bytes Register (Macaddrhi)
16 bits of the address to the MACADDRLO register. Since all eight addresses share the upper 40 bits of the address, the MACADDRHI register only needs to be written the first time. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 656: Transmit Channel N Dma Head Descriptor Pointer Register (Txnhdp)
Writing to these locations when they are nonzero is an error (except at reset). Host software must initialize these locations to 0 on reset. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 657: Transmit Channel N Completion Pointer Register (Txncp)
The EMAC uses the value written to determine if the interrupt should be deasserted. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 658: Statistics Register
Had no CRC error, alignment error, or code error Section 17.2.5.5 for definitions of alignment, code, and CRC errors. Overruns have no effect on this statistic. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 659 Overruns have no effect on this statistic. CRC alignment or code errors can be calculated by summing receive alignment errors, receive code errors, and receive CRC errors. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 660 The address matching process decided that the frame should be discarded (filtered) because it did not match the unicast, broadcast, or multicast address, and it did not match due to promiscuous mode. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 661 Any data or MAC control frame that was destined for any unicast, broadcast, or multicast address • Was any length • Had no late or excessive collisions, no carrier loss, and no underrun SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 662 • When the EMAC is in half-duplex mode, flow control is active, and a frame reception begins. CRC errors have no effect on this statistic. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 663 The number of frames sent by the EMAC that experienced FIFO underrun. Late collisions, CRC errors, carrier loss, and underrun have no effect on this statistic. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 664 Did not experience late collisions, excessive collisions, underrun, or carrier sense error • Was 128-bytes to 255-bytes long CRC errors, alignment/code errors, underruns, and overruns do not affect the recording of frames in this statistic. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 665 Error conditions such as alignment errors, CRC errors, code errors, overruns, and underruns do not affect the recording of bytes in this statistic. The objective of this statistic is to give a reasonable indication of Ethernet utilization. SPRUH90B – March 2013 EMAC/MDIO Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 666 (zero head descriptor pointer at the start or during the middle of the frame reception). CRC errors, alignment errors, and code errors have no effect on this statistic. EMAC/MDIO Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 667: External Memory Interface A (Emifa)
EMIFA SDRAM is supported on your device..........................Topic Page ....................18.1 Introduction ....................18.2 Architecture ..................18.3 Example Configuration ......................18.4 Registers SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 668: Introduction
The EMIFA SDRAM interface is not supported on all devices, see your device-specific data manual to see if the EMIFA SDRAM is supported on your device. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 669: Clock Control
When interfacing to an asynchronous device, this pin provides a signal which is active-low during the strobe period of an asynchronous write access cycle. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 670: Emifa Pins Specific To Sdram
EMA_A_RW EMIFA asynchronous read/write control. This pin stays high during reads and stays low during writes (same duration as CS). External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 671: Sdram Controller And Interface
EMA_RAS EMA_CAS EMA_WE EMA_BA[1:0] EMA_A[12:11] EMA_A[10] EMA_A[9:0] Bank/X ACTV Bank READ Bank Column Column Bank Column Column Mode Mode Mode REFR SLFR SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 672: Timing Waveform Of Sdram Pre Command
16-bit interface, refer to Table 18-6 for list of commonly-supported SDRAM devices and the required connections for the address pins. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 673: Emifa To 2M × 16 × 4 Bank Sdram Interface
A[11:0] EMIFA EMA_A[11:0] 128M bits ×16 SDRAM A[11:0] EMIFA EMA_A[11:0] 256M bits SDRAM A[12:0] EMIFA EMA_A[12:0] 512M bits SDRAM A[12:0] EMIFA EMA_A[12:0] SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 674: Description Of The Sdram Configuration Register (Sdcr)
/ (Required SDRAM Refresh Rate) EMA_CLK More information about the operation of the SDRAM refresh controller can be found in Section 18.2.4.6. 674 External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 675: Description Of The Sdram Timing Register (Sdtimr)
6. Finally, the EMIFA performs a refresh cycle, which consists of the following steps: (a) Issuing a PRE command with EMA_A[10] held high if any banks are open (b) Issuing an REF command SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 676: Sdram Load Mode Register Command
2. Program SDTIMR and SDSRETR to satisfy the timing requirements for the attached SDRAM device. The timing parameters should be taken from the SDRAM datasheet. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 677: Refresh Urgency Levels
Refresh Release urgency level is reached. At that point, the EMIFA can begin servicing any new read or write requests. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 678 EMA_CLK using the PLL Controller. If the frequency of EMA_CLK changes while the SDRAM is not in Self-Refresh Mode, Procedure B in Section 18.2.4.5 should be followed to reinitialize the device. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 679 If the PD bit is cleared while in the power-down state, the EMIFA will come out of the power-down state. The EMIFA: • Drives EMA_SDCKE high. • Enters its idle state. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 680: Timing Waveform For Basic Sdram Read Operation
NOP commands between various commands during an access. Refer to the register description of SDTIMR in Section 18.4.6 for more details on the various timing parameters. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 681: Timing Waveform For Basic Sdram Write Operation
NOP commands during various cycles of an access. Refer to the register description of SDTIMR in Section 18.4.6 for more details on the various timing parameters. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 682: Mapping From Logical Address To Emifa Pins For 16-Bit Sdram
EMA_BA[1:0] Column Address EMA_WE_DQM[0] NOTE: The upper bit of the Row Address is used only when addressing 256-Mbit and 512-Mbit SDRAM memories. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 683: Asynchronous Controller And Interface
EMA_CS[n], n = 2, 3, 4, or 5. Figure 18-7. EMIFA Asynchronous Interface EMIFA EMA_CS[n] EMA_WE EMA_OE EMA_WAIT EMA_D[x:0] EMA_WE_DQM[x:0] EMA_A[x:0] EMA_BA[1:0] SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 684: Emifa To 8-Bit/16-Bit Memory Interface
A[0] b) EMIF to 16-bit memory interface Figure 18-9. Common Asynchronous Interface EMIFA 16−bit asynchronous device EMA_CS[n] EMA_WE EMA_WE_DQM[1:0] BE[1:0] EMA_D[15:0] DQ[15:0] External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 685: Description Of The Asynchronous M Configuration Register (Cencfg)
The EMA_WAIT pin is not available on all devices; therefore, this field is reserved on those devices. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 686: Description Of The Asynchronous Wait Cycle Configuration Register (Awcc)
Extended Wait Mode should not be used while in NAND Flash Mode. The EMA_WAIT pin is not available on all devices; therefore, this register is reserved on those devices. 686 External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 687: Description Of The Emifa Interrupt Mask Set Register (Intmskset)
If so, the EMIFA proceeds to the setup period of the operation. If it is no longer the highest priority task, the EMIFA terminates the operation. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 688: Timing Waveform Of An Asynchronous Read Cycle In Normal Mode
Figure 18-10. Timing Waveform of an Asynchronous Read Cycle in Normal Mode Strobe Setup Hold EMA_CLK EMA_CS[n] EMA_WE_DQM Byte enable EMA_A/EMA_BA Address EMA_D Data EMA_OE EMA_WE External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 689: Asynchronous Write Operation In Normal Mode
If this is the case, the EMIFA instead enters directly into the turnaround period for the pending read or write operation. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 690: Timing Waveform Of An Asynchronous Write Cycle In Normal Mode
Figure 18-11. Timing Waveform of an Asynchronous Write Cycle in Normal Mode Strobe Setup Hold EMA_CLK EMA_CS[n] EMA_WE_DQM Byte enable EMA_A/EMA_BA Address Address Data EMA_D EMA_OE EMA_WE External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 691: Asynchronous Read Operation In Select Strobe Mode
If this is the case, the EMIFA instead enters directly into the turnaround period for the pending read or write operation. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 692: Timing Waveform Of An Asynchronous Read Cycle In Select Strobe Mode
Figure 18-12. Timing Waveform of an Asynchronous Read Cycle in Select Strobe Mode Strobe Setup Hold EMA_CLK EMA_CS[n] EMA_WE_DQM Byte enables EMA_A/EMA_BA Address EMA_D Data EMA_OE EMA_WE External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 693: Asynchronous Write Operation In Select Strobe Mode
If this is the case, the EMIFA instead enters directly into the turn-around period for the pending read or write operation. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 694: Timing Waveform Of An Asynchronous Write Cycle In Select Strobe Mode
Figure 18-13. Timing Waveform of an Asynchronous Write Cycle in Select Strobe Mode Strobe Setup Hold EMA_CLK EMA_CS[n] EMA_WE_DQM Byte enables EMA_A/EMA_BA Address EMA_D Data EMA_OE EMA_WE External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 695: Description Of The Nand Flash Control Register (Nandfcr)
NOTE: The EMIFA will not control the NAND Flash device's write protect pin. The write protect pin must be controlled outside of the EMIFA. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 696: Emifa To Nand Flash Interface
See Section 18.2.5.6.8 for workaround. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 697 NANDFCR. The NANDFmECC (m = 1, 2, 3, or 4) is cleared upon writing a 1 to the CSnECC (n = 2, 3, 4, or 5) bit. Figure 18-15 shows the algorithm used to calculate the ECC value for an 8-bit NAND Flash. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 698: Ecc Value For 8-Bit Nand Flash
If bit errors fall into more than four bytes, the ECC engine will report that there are too many errors to correct. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 699 15. Read the error value from the NAND Flash error value 1-2 registers (NANDERRVAL[2:1]). Errors can be corrected by XORing the error word with the error value from the NAND Flash error value 1-2 registers (NANDERRVAL[2:1]). SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 700 R_SETUP and R_STROBE fields must be greater than 4 for the EMIFA to recognize the EMA_WAIT pin has been asserted. The W_SETUP, W_STROBE, R_SETUP, and R_STROBE fields are in CEnCFG. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 701: Data Bus Parking
Power and Sleep Controller Figure 18-16. EMIFA Reset Block Diagram EMIFA CHIP_RST Hard Reset Memory from PLL Controller Registers State MOD_G_RST EMIFA Machine SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 702: Interrupt Support
See Section 18.4 for complete details on the register fields. 702 External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 703: Edma Event Support
For details on EMIFA pin multiplexing, see your device-specific data manual. 18.2.11 Memory Map For information describing the device memory-map, see your device-specific data manual. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 704: Priority And Arbitration
See Section 18.2.4.7 for details on the operation of the EMIFA when in the self-refresh state. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 705: System Considerations
The system should be analyzed to make sure that this worst-case request delay is acceptable. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 706: Power Management
EMA_SDCKE remains low until any request arrives. Refer to Section 18.2.4.8 for more details on placing EMIFA in power down mode. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 707: Emulation Considerations
Now EMIFA memory controller is in the enable state and continues with normal operation. 18.2.15 Emulation Considerations EMIFA memory controller will remain fully functional during emulation halts, to allow emulation access to external memory. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 708: Example Configuration
Table 18-26. SR Field Value For the EMIFA to K4S641632H-TC(L)70 Interface Field Value Purpose 1 then 0 To place the EMIFA into the self refresh state External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 709: Example Configuration Interface
BA[1] EMA_BA[1] EMA_BA[0] BA[0] EMA_A[18:0] A[11:0] LDQM EMA_WE_DQM[0] UDQM EMA_WE_DQM[1] DQ[15:0] EMA_D[15:0] EMA_CS[3] EMA_OE TC5515100FT-12 EMA_WAIT A[0] A[19:1] DQ[15:0] RY/BY BYTE0 BYTE1 SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 710: Sdram Timing Register (Sdtimr)
Figure 18-19. SDRAM Timing Register (SDTIMR) 0 0110 T_RFC T_RP Rsvd T_RCD Rsvd T_WR 0100 0110 0000 T_RAS T_RC Rsvd T_RRD Reserved External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 711: Sdram Self Refresh Exit Timing Register (Sdsretr)
= 100 MHz EMA_CLK Figure 18-21. SDRAM Refresh Control Register (SDRCR) 0 0000 0000 0000 Reserved Reserved 0 0110 0001 1010 (61Ah) Reserved SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 712: Sdram Configuration Register (Sdcr)
Figure 18-22. SDRAM Configuration Register (SDCR) 0 0000 Reserved Reserved Reserved 00 0000 Reserved Reserved Reserved Reserved Reserved Reserved BIT11_9LOCK Reserved IBANK Reserved PAGESIZE External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 713: Emifa Input Timing Requirements
R_SETUP width in EMIFA clock cycles minus 1 cycle. R_SETUP + R_STROBE ≥ R_SETUP ) R_STROBE ) R_HOLD w R_HOLD w SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 714: Timing Waveform Of An Asram Read
Description Write Pulse width Address valid to end of Write Data Setup time Write Recovery time Data Hold time Write Cycle time External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 715: Timing Waveform Of An Asram Write
W_SETUP ) W_STROBE ) W_HOLD w Figure 18-24. Timing Waveform of an ASRAM Write Setup Hold Strobe EMA_CS[n] EMA_A[x:0] EMA_BA[1:0] EMA_WE EMA_D[x:0] SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 716: Asram Timing Requirements With Pcb Delays
R_SETUP + R_STROBE ≥ R_SETUP ) R_STROBE ) R_HOLD w (m) * t EM_D EM_A R_HOLD w (m) ) t EM_CS EM_D TA w External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 717: Timing Waveform Of An Asram Read With Pcb Delays
CEnCFG is programmed in terms of EMIFA clock cycles, minus 1 cycle. For example, W_SETUP is equal to W_SETUP width in EMIFA clock cycles minus 1 cycle. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 718: Timing Waveform Of An Asram Write With Pcb Delays
EMA_CS[n] EMA_CS EMA_CS EMA_CS[n] (ASRAM) EMA_A[x:0]/ EMA_BA[1:0] EMA_A EMA_A EMA_A[x:0]/ EMA_BA[1:0] (ASRAM) EMA_WE EMA_WE EMA_WE EMA_WE (ASRAM) EMA_D[x:0] EMA_D EMA_D EMA_D[x:0] (ASRAM) External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 719: Emifa Timing Requirements For Tc5516100Ft-12 Example
Delay on EMA_WE from EMIFA to ASRAM. EMA_WE is driven by EMIF. 0.36 EM_WE Delay on EMA_D from EMIFA to ASRAM. EMA_D is driven by EMIF. 0.45 EM_D SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 720 W_SETUP ) W_STROBE ) W_HOLD w * 3 w * 3 w * 1.8 Therefore, W_SETUP = 0, W_STROBE = 0, and W_HOLD = 0. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 721: Configuring Ce3Cfg For Tc5516100Ft-12 Example
Table 18-40. Recommended Margins Timing Parameter Recommended Margin Output Setup 10 nS Output Hold 10 nS Input Setup 10 nS Input Hold 10 nS SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 722: Emifa Read Timing Requirements
EMIFA and NAND Flash AC timing requirements work together to define the values for R_SETUP, R_STROBE, and R_HOLD. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 723: Timing Waveform Of A Nand Flash Read
(m) * (R_HOLD ) 1)t TA w max Figure 18-27. Timing Waveform of a NAND Flash Read Setup Hold Strobe EMA_CS[n] ALE_EM_A[1] CLE_EM_A[2] EMA_OE EMA_D[7:0] SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 724: Nand Flash Write Timing Requirements
W_SETUP is equal to W_SETUP width in EMIFA clock cycles minus 1 cycle. W_SETUP w max W_STROBE w W_SETUP + W_STROBE ≥ W_HOLD w max W_SETUP ) W_STROBE ) W_HOLD w External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 725: Timing Waveform Of A Nand Flash Command Write
ALE_EM_A[1] CLE_EM_A[2] EMA_WE EMA_D[7:0] Figure 18-29. Timing Waveform of a NAND Flash Address Write Setup Hold Strobe EMA_CS[n] ALE_EM_A[1] CLE_EM_A[2] EMA_WE EMA_D[7:0] SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 726: Timing Waveform Of A Nand Flash Data Write
Example Configuration www.ti.com Figure 18-30. Timing Waveform of a NAND Flash Data Write Setup Hold Strobe EMA_CS[n] ALE_EM_A[1] CLE_EM_A[2] EMA_WE EMA_D[7:0] External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 727: Emifa Timing Requirements For Hy27Ua081G1M Example
ALE Setup time CS Setup time Data Setup time CLE Hold time ALE Hold time CS Hold time Data Hold time Write Cycle time SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 728 * 3 w 5 Therefore with a 10 nS margin added in, W_SETUP ≥ 0, W_STROBE ≥ 6, and W_HOLD ≥ 1. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 729: Configuring Ce2Cfg For Hy27Ua081G1M Example
• CS3NAND = 0. NAND Flash mode is disabled. CS2NAND NAND Flash mode for chip select 2. • CS5NAND = 1. NAND Flash mode is enabled. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 730: Registers
NANDERRVAL1 NAND Flash 4-Bit ECC Error Value Register 1 Section 18.4.22 NANDERRVAL2 NAND Flash 4-Bit ECC Error Value Register 2 Section 18.4.23 External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 731: Module Id Register (Midr)
R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 Reserved MAX_EXT_WAIT R/W-80h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 732: Asynchronous Wait Cycle Configuration Register (Awccr) Field Descriptions
Maximum extended wait cycles. The EMIFA will wait for a maximum of (MAX_EXT_WAIT + 1) × 16 clock cycles before it stops inserting asynchronous wait cycles and proceeds to the hold period of the access. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 733: Sdram Configuration Register (Sdcr)
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default value of 0. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 734 9 column address bits (512 elements per row) 10 column address bits (1024 elements per row) 11 column address bits (2048 elements per row) 4h-7h Reserved External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 735: Sdram Refresh Control Register (Sdrcr)
Writing a value < 0x0020 to this field will cause it to be loaded with (2 × T_RFC) + 1 value from the SDRAM timing register (SDTIMR). SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 736: Asynchronous N Configuration Registers (Ce2Cfg-Ce5Cfg)
Asynchronous Data Bus Width. This field defines the width of the asynchronous device's data bus. 8-bit data bus 16-bit data bus 2h-3h Reserved External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 737: Sdram Timing Register (Sdtimr)
Reserved. The reserved bit location is always read as 0. If writing to this field, always write the default value of 0. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 738: Sdram Self Refresh Exit Timing Register (Sdsretr)
This field specifies the minimum number of ECLKOUT cycles from Self-Refresh exit to any command, minus one. T_XS = Txsr / t EMA_CLK External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 739: Emifa Interrupt Raw Register (Intraw)
Indicates that an Asynchronous Timeout has occurred. Writing a 1 will clear this bit as well as the AT_MASKED bit in the EMIFA interrupt masked register (INTMSK). SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 740: Emifa Interrupt Masked Register (Intmsk)
Indicates that an Asynchronous Timeout Interrupt has been generated. Writing a 1 will clear this bit as well as the AT bit in the EMIFA interrupt raw register (INTRAW). External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 741: Emifa Interrupt Mask Set Register (Intmskset)
Indicates that the Asynchronous Timeout Interrupt is enabled. Writing a 1 sets this bit and the AT_MASK_CLR bit in the EMIFA interrupt mask clear register (INTMSKCLR). SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 742: Emifa Interrupt Mask Clear Register (Intmskclr)
Indicates that the Asynchronous Timeout Interrupt is enabled. Writing a 1 clears this bit and the AT_MASK_SET bit in the EMIFA interrupt mask set register (INTMSKSET). External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 743: Nand Flash Control Register (Nandfcr)
NAND Flash ECC start for chip select 2. This bit is cleared when CS2 1_bit ECC register is read. Do not start ECC calculation. Start ECC calculation on data for NAND Flash on EMA_CS2. Reserved Reserved SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 744 Using NAND Flash on EMA_CS3. CS2NAND NAND Flash mode for chip select 2. Not using NAND Flash. Using NAND Flash on EMA_CS2. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 745: Nand Flash Status Register (Nandfsr)
(AWCC) has no effect on WAITST. EMA_WAIT[n] pin is low. EMA_WAIT[n] pin is high. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 746: Nand Flash N Ecc Registers (Nandf1Ecc-Nandf4Ecc)
ECC code calculated while reading/writing NAND Flash. ECC code calculated while reading/writing NAND Flash. ECC code calculated while reading/writing NAND Flash. ECC code calculated while reading/writing NAND Flash. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 747: Nand Flash 4-Bit Ecc Load Register (Nand4Biteccload)
Reserved 4BITECCLOAD 0-3FFh 4-bit ECC load. This value is used to load the ECC values when performing the Syndrome calculation during reads. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 748: Nand Flash 4-Bit Ecc Register 1 (Nand4Bitecc1)
Reserved Reserved 25-16 4BITECCVAL4 0-3FFh Calculated 4-bit ECC or Syndrom Value4. 15-10 Reserved Reserved 4BITECCVAL3 0-3FFh Calculated 4-bit ECC or Syndrom Value3. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 749: Nand Flash 4-Bit Ecc Register 3 (Nand4Bitecc3)
Reserved Reserved 25-16 4BITECCVAL8 0-3FFh Calculated 4-bit ECC or Syndrom Value8. 15-10 Reserved Reserved 4BITECCVAL7 0-3FFh Calculated 4-bit ECC or Syndrom Value7. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 750: Nand Flash 4-Bit Ecc Error Address Register 1 (Nanderradd1)
Reserved Reserved 25-16 4BITECCERRADD4 0-3FFh Calculated 4-bit ECC Error Address 4. 15-10 Reserved Reserved 4BITECCERRADD3 0-3FFh Calculated 4-bit ECC Error Address 3. External Memory Interface A (EMIFA) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 751: Nand Flash 4-Bit Ecc Error Value Register 1 (Nanderrval1)
Reserved Reserved 25-16 4BITECCERRVAL4 0-3FFh Calculated 4-bit ECC Error Value 4. 15-10 Reserved Reserved 4BITECCERRVAL3 0-3FFh Calculated 4-bit ECC Error Value 3. SPRUH90B – March 2013 External Memory Interface A (EMIFA) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 752: External Memory Interface B (Emifb)
This chapter describes the external memory interface B (EMIFB)..........................Topic Page ....................19.1 Introduction ....................19.2 Architecture ..................19.3 Example Configuration ......................19.4 Registers External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 753: Introduction
EMB_CS EMB_CAS EDMA Cmd/Write EMB_RAS Crossbar FIFO EMB_WE Master EMB_CLK SDRAM Peripherals Interface EMB_SDCKE Read (USB, UHPI...) EMB_BA[1:0] FIFO EMB_A[x:0] EMB_D[x:0] EMB_WE_DQM[x:0] SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 754: Architecture
This pin is connected to the RAS pin of the attached SDRAM device and is used for sending commands to the device. 754 External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 755: Pin Multiplexing
No operation. The NOP command is issued during all cycles in which one of the above commands is not issued. SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 756: Timing Waveform Of Sdram Pre Command
REFR SLFR Figure 19-2. Timing Waveform of SDRAM PRE Command EMB_CLK EMB_CS EMB_WE_DQM EMB_BA Bank EMB_A[10] = 0 EMB_A EMB_RAS EMB_CAS EMB_WE External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 757: Emifb To 2M × 16 × 4 Bank Sdram Interface
SDRAM EMIFB 2M x 32 x 4 Bank EMB_CS EMB_CAS EMB_RAS EMB_WE EMB_CLK EMB_SDCKE EMB_BA[1:0] BA[1:0] EMB_A[11:0] A[11:0] EMB_WE_DQM[3:0] DQM[3:0] EMB_D[31:0] DQ[31:0] SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 758: Emifb To Dual 4M × 16 × 4 Bank Sdram Interface
SDRAM A[12:0] EMIFB EMB_A[12:0] ×32 SDRAM A[11:0] EMIFB EMB_A[11:0] 512M bits ×16 SDRAM A[12:0] EMIFB EMB_A[12:0] ×32 SDRAM A[12:0] EMIFB EMB_A[12:0] 758 External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 759: Example Of 16-Bit Emifb Address Pin Connections
• When IBANK = 2h, 4 internal banks are used This field value affects the mapping of logical addresses to SDRAM row, column, and bank addresses. See Section 19.2.6.12 for details. SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 760: Description Of The Sdram Refresh Control Register (Sdrfc)
The T_CKE field fixes the minimum time between CKE transitions. This parameter is set to satisfy the value for the attached SDRAM device. 760 External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 761: Description Of The Sdram Configuration 2 Register (Sdcfg2)
0 (Internal Temperature These bits are set according to the PASR field in the drive strength) Compensated Self Refresh) SDRAM configuration 2 register (SDCFG2). SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 762: Sdram/Mobile Sdram Load Mode Register Command
SDRAM. The remainder of this section details the EMIFB's refresh scheme and provides an example for determining the appropriate value to place in the REFRESH_RATE field of SDRFC. External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 763: Refresh Urgency Levels
REFRESH_RATE can be calculated as: REFRESH_RATE = 133 MHz × 64 ms/8192 REFRESH_RATE = 1039.06 REFRESH_RATE = 1039 cycles = 40Fh cycles SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 764 (driving EMB_SDCKE high) and executes the requests; after which it again goes back to the power- down state (driving EMB_SDCKE low). External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 765: Pasr Bitfield In Sdram Configuration 2 Register (Sdcfg2) Configuration
Refresh banks 0, 1, 2, and 3 Refresh banks 0 and 1 Refresh bank 0 Reserved Reserved Refresh 1/2 of bank 0 Refresh 1/4 of bank 0 Reserved SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 766: Timing Waveform For Basic Sdram Read Operation
NOP commands between various commands during an access. Refer to the register description of SDTIM1 and SDTIM2 for more details on the various timing parameters. External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 767: Timing Waveform For Basic Sdram Write Operation
NOP commands during various cycles of an access. Refer to the register description of SDTIM1 and SDTIM2 for more details on the various timing parameters. SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 768: Example Mapping From Logical Address To Emifb Pins For 32-Bit Sdram
BA[1:0] Column Address WE_DQM[3:0] Row Address Column Address WE_DQM[3:0] Row Address BA[0] Column Address WE_DQM[3:0] Row Address BA[1:0] Column Address WE_DQM[3:0] 768 External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 769: Example Mapping From Logical Address To Emifb Pins For 16-Bit Sdram
PAGESIZE = 2 => 10 bits ROWSIZE = 3 => 12 bits PAGESIZE = 3 => 11 bits ROWSIZE = 4 => 13 bits SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 770: Emifb Memory Controller Fifo Block Diagram
Command/data Command Command FIFO scheduler to memory Write FIFO Write Data to memory Read FIFO Read data from memory Registers Command Data External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 771 From the same master, any read to the same location (or within 2048 bytes) as a previous write will complete in order SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 772 The EDMA peripheral does not need to implement the above workaround. If a peripheral is not listed here, then the above workaround is required. External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 773: Reset And Initialization Considerations
EMIFB memory controller is a DMA slave peripheral and therefore does not generate DMA events. Data read and write requests may be made directly, by masters and the DMA. SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 774: Power Management
EMB_SDCKE remains low until any request arrives. Refer to Section 19.2.6.8 for more details on placing EMIFB in power-down mode. External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 775 Bring EMIFB out of self-refresh mode. Refer to Section 19.2.6.7 for details on self-refresh mode. After auto wake, EMIFB is in enable state and clocks run continuously. SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 776: Emulation Considerations
SYSCLK domain of the PLL Controller. Once the PLL has been reprogrammed, remove the SDRAM from Self-Refresh by clearing the LP_MODE bit in SDRFC. External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 777: Connecting Emifb Memory Controller For 32-Bit Connection
4M x 16 x 4 Bank EMB_CS EMB_CAS EMB_RAS EMB_WE EMB_CLK EMB_SDCKE EMB_BA[1:0] BA[1:0] EMB_A[12:0] A[12:0] EMB_WE_DQM[0] LDQM EMB_WE_DQM[1] UDQM EMB_D[15:0] DQ[15:0] SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 778: Sdcfg Configuration
This bit is ignored when LP_MODE=0. REFRESH_RATE 40Eh Set to 40Eh SDRAM clock cycles to meet the SDRAM memory refresh rate requirement. External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 779: Sdtim1 Configuration
) - 1 EMB_CLK EMB_CKE changes Register field value must be ≤ the calculated value Register field value must be ≥ the calculated value SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 780: Registers
LEGEND: R = Read only; -n = value after reset Table 19-25. Revision ID Register (REVID) Field Descriptions Field Value Description 31-0 4033 131Fh Revision ID value of EMIFB. External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 781: Sdram Configuration Register (Sdcfg)
When this bit is 1 and SDREN = 1, then mSDR is enabled. Reserved All writes to these bit(s) must always have a value of 0. SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 782 512-word pages requiring 9 column address bits. 1024-word pages requiring 10 column address bits. 2048-word pages requiring 11 column address bits. 4h-7h Reserved External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 783: Sdram Refresh Control Register (Sdrfc)
Writing a value < 0100h to this field causes it to be loaded with 2 × T_RFC value from SDRAM timing 1 register (SDTIM1). The required refresh rate is derived from the SDRAM device data sheet. SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 784: Sdram Timing 1 Register (Sdtim1)
) + (2 × t )) / (4 × t ) - 1. Reserved All writes to these bit(s) must always have a value of 0. External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 785: Sdram Timing 2 Register (Sdtim2)
Minimum number of EMB_CLK cycles between EMB_SDCKE changes, minus one. This field must satisfy t for the SDRAM device. T_CKE = (t /EMIF_CLK) - 1 SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 786: Sdram Configuration 2 Register (Sdcfg2)
11 row address bits used. 12 row address bits used. 13 row address bits used. 14 row address bits used. 6h-7h Reserved External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 787: Peripheral Bus Burst Priority Register (Bprio)
Recommended setting for typical system operation is between 10h and 20h. SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 788: Performance Counter 1 Register (Pc1)
32-bit counter that can be configured as specified in the performance counter configuration register (PCC) and the performance counter master region select register. External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 789: Performance Counter Configuration Register (Pcc)
Any writes to these bit(s) must always have a value of 0. CNTR1_CFG 0-Fh Filter configuration for performance counter 1 register (PC1). Refer to Table 19-35 details. SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 790: Performance Counter Filter Configuration
As the value of this counter approaches 100%, the number of cycles the EMIFB has a command in the command FIFO to service approaches 100%. Ah-Fh Reserved External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 791: Performance Counter Master Region Select Register (Pcmrs)
Region select for performance counter 1 register (PC1). PC1 counts total SDRAM accesses. 1h-6h Reserved PC1 counts total EMIFB memory-mapped register accesses. 8h-Fh Reserved SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 792: Performance Counter Time Register (Pct)
Line trap has occurred due to use of unsupported addressing mode. EMIFB supports linear incrementing and cache line wrap addressing modes. Reserved All writes to these bit(s) must always have a value of 0. External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 793: Interrupt Mask Register (Imr)
Line trap occurred due to use of unsupported addressing mode (only set if the LTMSET bit in IMSR is set). Reserved All writes to these bit(s) must always have a value of 0. SPRUH90B – March 2013 External Memory Interface B (EMIFB) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 794: Interrupt Mask Set Register (Imsr)
Line trap interrupt is enabled; a write of 1 to the LTMSET bit in IMSR occurred. Reserved All writes to these bit(s) must always have a value of 0. External Memory Interface B (EMIFB) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 795: General-Purpose Input/Output (Gpio)
When configured as an input, you can detect the state of the input by reading the state of an internal register. This chapter describes the GPIO..........................Topic Page ....................20.1 Introduction ....................20.2 Architecture ......................20.3 Registers SPRUH90B – March 2013 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 796: Introduction
The GPIO peripheral connects to external devices. While it is possible that the software implements some standard connectivity protocol over GPIO, the GPIO peripheral itself is not compliant with any such standards. General-Purpose Input/Output (GPIO) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 797: Architecture
GPIO module. 20.2.4 Endianness Considerations The GPIO operation is independent of endianness; therefore, there are no endianness considerations for the GPIO module. SPRUH90B – March 2013 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 798: Gpio Register Structure
Bit 25 GP1P9 GP1[10] register_name01 Bit 26 GP1P10 GP1[11] register_name01 Bit 27 GP1P11 GP1[12] register_name01 Bit 28 GP1P12 GP1[13] register_name01 Bit 29 GP1P13 798 General-Purpose Input/Output (GPIO) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 799 Bit 8 GP4P8 GP4[9] register_name45 Bit 9 GP4P9 GP4[10] register_name45 Bit 10 GP4P10 GP4[11] register_name45 Bit 11 GP4P11 GP4[12] register_name45 Bit 12 GP4P12 SPRUH90B – March 2013 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 800 Bit 23 GP7P7 GP7[8] register_name67 Bit 24 GP7P8 GP7[9] register_name67 Bit 25 GP7P9 GP7[10] register_name67 Bit 26 GP7P10 GP7[11] register_name67 Bit 27 GP7P11 800 General-Purpose Input/Output (GPIO) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 801: Using A Gpio Signal As An Output
GPIO input data register (IN_DATA) associated with the desired GPIO signal. IN_DATA contains the actual logic state on the external signal. For detailed information on these registers, see Section 20.3. SPRUH90B – March 2013 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 802: Using A Gpio Signal As An Input
PSC reset, followed by GPIO clock enable) will result in the default configuration register settings. For details on the PSC, see the Power and Sleep Controller (PSC) chapter. General-Purpose Input/Output (GPIO) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 803: Initialization
To configure a GPIO interrupt to occur only on falling edges of the GPIO signal: • Write a logic 1 to the associated bit in SET_FAL_TRIG. • Write a logic 1 to the associated bit in CLR_RIS_TRIG. SPRUH90B – March 2013 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 804: Edma Event Support
GPIO signals configured as outputs are maintained at their state prior to the GPIO peripheral entering the low-power state. 20.2.13 Emulation Considerations The GPIO peripheral is not affected by emulation suspend events (such as halts and breakpoints). General-Purpose Input/Output (GPIO) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 805: Registers
CLR_FAL_TRIG45 GPIO Banks 4 and 5 Clear Falling Edge Interrupt Register Section 20.3.11 INTSTAT45 GPIO Banks 4 and 5 Interrupt Status Register Section 20.3.12 SPRUH90B – March 2013 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 806: Revision Id Register (Revid)
LEGEND: R = Read only; -n = value after reset Table 20-3. Revision ID Register (REVID) Field Descriptions Field Value Description 31-0 4483 0105h Peripheral Revision General-Purpose Input/Output (GPIO) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 807: Gpio Interrupt Per-Bank Enable Register (Binten)
Bank 0 interrupt enable is used to disable or enable the bank 0 interrupts (events from GP0[15-0]). Bank 0 interrupts are disabled. Bank 0 interrupts are enabled. SPRUH90B – March 2013 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 808: Gpio Direction Registers (Dirn)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-1 LEGEND: R/W = Read/Write; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 809: Gpio Bank 8 Direction Register (Dir8)
Direction of pin GPk[j]. The GPkPj bit is used to control the direction (output = 0, input = 1) of pin j in GPIO bankk. GPk[j] is an output. GPk[j] is an input. SPRUH90B – March 2013 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 810: Gpio Output Data Registers (Out_Datan)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 811: Gpio Output Data Register (Out_Datan) Field Descriptions
Output drive state of GPk[j]. The GPkPj bit is used to drive the output (low = 0, high = 1) of pin j in GPIO bankk. The GPkPj bit is ignored when GPk[j] is configured as an input. GPk[j] is driven low. GPk[j] is driven high. SPRUH90B – March 2013 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 812: Gpio Set Data Registers (Set_Datan)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 813: Gpio Set Data Register (Set_Datan) Field Descriptions
GPIO bankk. The GPkPj bit is ignored when GPk[j] is configured as an input. Reading the GPkPj bit returns the output drive state of GPk[j]. No effect. GPk[j] is set to output logic high. SPRUH90B – March 2013 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 814: Gpio Clear Data Registers (Clr_Datan)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 815: Gpio Clear Data Register (Clr_Datan) Field Descriptions
GPIO bankk. The GPkPj bit is ignored when GPk[j] is configured as an input. Reading the GPkPj bit returns the output drive state of GPk[j]. No effect. GPk[j] is set to output logic low. SPRUH90B – March 2013 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 816: Gpio Input Data Registers (In_Datan)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 LEGEND: R = Read only; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 817: Gpio Input Data Register (In_Datan) Field Descriptions
Status of pin GPk[j]. Reading the GPkPj bit returns the state of pin j in GPIO bank k. GPk[j] is logic low. GPk[j] is logic high. SPRUH90B – March 2013 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 818: Gpio Set Rising Edge Interrupt Registers (Set_Ris_Trign)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 819: Gpio Set Rising Edge Trigger Interrupt Register (Set_Ris_Trign) Field Descriptions
No effect. Interrupt is caused by a low-to-high transition on GPk[j]. SPRUH90B – March 2013 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 820: Gpio Clear Rising Edge Interrupt Registers (Clr_Ris_Trign)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 821: Gpio Clear Rising Edge Interrupt Register (Clr_Ris_Trign) Field Descriptions
GPk[j]. Therefore, this bit will be one in both registers if the function is enabled, and zero in both registers if the function is disabled. No effect. No interrupt is caused by a low-to-high transition on GPk[j]. SPRUH90B – March 2013 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 822: Gpio Set Falling Edge Interrupt Registers (Set_Fal_Trign)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 823: Gpio Set Falling Edge Trigger Interrupt Register (Set_Fal_Trign) Field Descriptions
No effect. Interrupt is caused by a high-to-low transition on GPk[j]. SPRUH90B – March 2013 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 824: Gpio Clear Falling Edge Interrupt Registers (Clr_Fal_Trign)
GP6P15 GP6P14 GP6P13 GP6P12 GP6P11 GP6P10 GP6P9 GP6P8 GP6P7 GP6P6 GP6P5 GP6P4 GP6P3 GP6P2 GP6P1 GP6P0 R/W-0 LEGEND: R/W = Read/Write; -n = value after reset General-Purpose Input/Output (GPIO) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 825: Gpio Clear Falling Edge Interrupt Register (Clr_Fal_Trign) Field Descriptions
GPk[j]. Therefore, this bit will be one in both registers if the function is enabled, and zero in both registers if the function is disabled. No effect. No interrupt is caused by a high-to-low transition on GPk[j]. SPRUH90B – March 2013 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 826: Gpio Interrupt Status Registers (Intstatn)
GP6P1 GP6P0 R/W1C-0 LEGEND: R/W = Read/Write; W1C = Write 1 to clear bit (writing 0 has no effect); -n = value after reset General-Purpose Input/Output (GPIO) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 827: Gpio Bank 8 Interrupt Status Register (Intstat8)
Write a 1 to the GPkPj bit to clear the status bit; a write of 0 has no effect. No pending interrupt on GPk[j]. Pending interrupt on GPk[j]. SPRUH90B – March 2013 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 828: Inter-Integrated Circuit (I2C) Module
Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1..........................Topic Page ....................21.1 Introduction ....................21.2 Architecture ......................21.3 Registers Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 829: Introduction
The combined format in 10-bit addressing mode (the I2C sends the slave address the second byte every time it sends the slave address the first byte). SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 830: Functional Block Diagram
ICXEVT EDMA controller 21.1.4 Industry Standard(s) Compliance Statement The I2C peripheral is compliant with the Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1. Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 831: Architecture
Figure 21-2. Figure 21-2. Multiple I2C Modules Connected TI device Pull-up resistors controller Serial data (I2Cx_SDA) Serial clock (I2Cx_SCL) TI device EPROM SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 832: Clock Generation
The I2C module must be operated with a prescaled module clock frequency of 6.7 to 13.3 MHz. The I2C prescaler register (ICPSC) must be configured to this frequency range. Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 833: Clock Synchronization
I2C-bus, the levels of logic 0 (low) and logic 1 (high) are not fixed and depend on the associated power supply level. See your device-specific data manual for more information. SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 834: Start And Stop Conditions
(including the MST, STT, and STP bits). Figure 21-6. I2C Peripheral START and STOP Conditions I2Cx_SDA I2Cx_SCL START STOP condition (S) condition (P) Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 835: Serial Data Formats
ACK P n = The number of data bits (from 1 to 8) specified by the bit count (BC) field of ICM DR. SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 836: I2C Peripheral 10-Bit Addressing Format With Master-Transmitter Writing To Slave-Receiver (Fdf = 0, Xa = 1 In Icmdr)
Any number number n = The number of data bits (from 1 to 8) specified by the bit count (BC) field of ICMDR. Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 837: Operating Modes
I2C peripheral on I2Cx_SCL. The clock pulses are inhibited and I2Cx_SCL is held low when the intervention of the processor is required (XSMT = 0 in ICSTR) after data has been transmitted. SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 838: Nack Bit Generation
• If STP = 0, make STP = 1 to generate a STOP condition. • Reset the peripheral (IRS = 0 in ICMDR). Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 839: Arbitration
Figure 21-12. Arbitration Procedure Between Two Master-Transmitters Bus line I2Cx_SCL Device #1 lost arbitration and switches off Data from device #1 Data from device #2 Bus line I2Cx_SDA SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 840: Reset Considerations
Once the bus is determined to be available (the bus is not busy), the I2C is ready to proceed with the desired communication. Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 841: Interrupt Support
If there is more than one pending interrupt flag, reading ICIVR clears the highest-priority interrupt flag. SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 842: Dma Events Generated By The I2C Peripheral
I2C peripheral is acting as a master or a slave. For more information, see the description of the FREE bit in ICMDR (see Section 21.3.9). Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 843: Registers
I2C Pin Data Out Register Section 21.3.19 ICPDSET I2C Pin Data Set Register Section 21.3.20 ICPDCLR I2C Pin Data Clear Register Section 21.3.21 SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 844: I2C Own Address Register (Icoar)
In 7-bit addressing mode (XA = 0 in ICMDR): bits 6-0 provide the 7-bit slave address of the I2C. Bits 9-7 are ignored. In 10-bit addressing mode (XA = 1 in ICMDR): bits 9-0 provide the 10-bit slave address of the I2C. Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 845: I2C Interrupt Mask Register (Icimr)
No-acknowledgment interrupt enable bit. Interrupt request is disabled. Interrupt request is enabled. Arbitration-lost interrupt enable bit Interrupt request is disabled. Interrupt request is enabled. SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 846: I2C Interrupt Status Register (Icstr)
• The I2C is reset (either when 0 is written to the IRS bit of ICMDR or when the processor is reset). Overrun is detected. Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 847 0). • In the repeat mode (RM = 1): ARDY is set at the end of each data word transmitted from ICDXR. SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 848 • The I2C attempts to start a transfer while the BB (bus busy) bit is set to 1. When AL is set to 1, the MST and STP bits of ICMDR are cleared, and the I2C becomes a slave- receiver. Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 849: I2C Clock Divider Registers (Icclkl And Icclkh)
Clock high-time divide-down value of 1-65536. The period of the module clock is multiplied by (ICCH + d) to produce the high-time duration of the I2C serial on the I2Cx_SCL pin. SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 850: I2C Data Count Register (Iccnt)
ICMDR, a STOP condition is generated when the internal data counter counts down to 0. The start value loaded to the internal data counter is 65536. 1h-FFFFh The start value loaded to internal data counter is 1-65535. Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 851: I2C Data Receive Register (Icdrr)
31-8 Reserved These reserved bit locations are always read as zeros. A value written to this field has no effect. 0-FFh Receive data. SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 852: I2C Slave Address Register (Icsar)
In 10-bit addressing mode (XA = 1 in ICMDR): Bits 9-0 provide the 10-bit slave address that the I2C transmits when it is in the master-transmitter mode. Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 853: I2C Data Transmit Register (Icdxr)
31-8 Reserved These reserved bit locations are always read as zeros. A value written to this field has no effect. 0-FFh Transmit data. SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 854: I2C Mode Register (Icmdr)
STP is automatically cleared after the STOP condition has been generated. STP has been set to generate a STOP condition when the internal data counter of the I2C counts down to 0. Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 855 Free data format mode is disabled. Transfers use the 7-/10-bit addressing format selected by the XA bit. Free data format mode is enabled. SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 856: Master-Transmitter/Receiver Bus Activity Defined By Rm, Stt, And Stp Bits
TRX identifies the role of the I2C: TRX = 0: The I2C is a receiver. TRX = 1: The I2C is a transmitter. 856 Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 857: Block Diagram Showing The Effects Of The Digital Loopback Mode (Dlb) Bit
To CPU or EDMA ICDRR ICRSR From CPU or EDMA ICSAR From CPU or EDMA ICOAR ICXSR From CPU or EDMA ICDXR Address/data SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 858: I2C Interrupt Vector Register (Icivr)
Register-access-ready interrupt (ARDY) Receive-data-ready interrupt (ICRRDY) Transmit-data-ready interrupt (ICXRDY) Stop condition detected interrupt (SCD) Address-as-slave interrupt (AAS). Lowest priority if multiple I2C interrupts are pending. Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 859: I2C Extended Mode Register (Icemdr)
The transmit data ready interrupt is generated when the data in ICDXR is copied to ICXSR. SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 860: I2C Prescaler Register (Icpsc)
I2C clock frequency = I2C input clock frequency/(IPSC + 1) Note: IPSC must be initialized while the I2C is in reset (IRS = 0 in ICMDR). Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 861: I2C Revision Identification Register (Revid1)
LEGEND: R = Read only; -n = value after reset Table 21-21. I2C Revision Identification Register 2 (REVID2) Field Descriptions Field Value Description 31-0 REVID2 Peripheral Identification Number SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 862: I2C Dma Control Register (Icdmac)
Receive DMA enable . This bit controls the receive DMA event pin to the system. Always set this bit to DMA receive event is disabled. DMA receive event is enabled. Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 863: I2C Pin Function Register (Icpfunc)
1 regardless of PFUNC0, and the I2C function works whenever the IRS bit is 1. You are expected to hold I2C in reset via the IRS bit when changing to/from GPIO mode via the PFUNC0 bit. SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 864: I2C Pin Direction Register (Icpdir)
I2Cx_SDA pin functions as output. PDIR0 Controls the direction of the I2Cx_SCL pin when configured as GPIO. I2Cx_SCL pin functions as input. I2Cx_SCL pin functions as output. Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 865: I2C Pin Data In Register (Icpdin)
Logic-low present at I2Cx_SCL pin, regardless of PFUNC bit setting. Logic-high present at I2Cx_SCL pin, regardless of PFUNC bit setting. During writes: Writes have no effect. SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 866: I2C Pin Data Out Register (Icpdout)
I2C cannot drive I2Cx_SCL to high. During reads: Reads return register values, not GPIO pin levels. During writes: I2Cx_SCL pin is driven low. I2Cx_SCL pin is driven high. Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 867: I2C Pin Data Set Register (Icpdset)
Used to set the PDOUT0 bit in the I2C pin data out register (ICPDOUT) that corresponds to the I2Cx_SCL GPIO pin. During reads: Reads return indeterminate values. During writes: No effect PDOUT0 bit is set to logic high. SPRUH90B – March 2013 Inter-Integrated Circuit (I2C) Module Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 868: I2C Pin Data Clear Register (Icpdclr)
Used to clear the PDOUT0 bit in the I2C pin data out register (ICPDOUT) that corresponds to the I2Cx_SCL GPIO pin. During reads: Reads return indeterminate values. During writes: No effect PDOUT0 bit is cleared to logic low. Inter-Integrated Circuit (I2C) Module SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 869: Multichannel Audio Serial Port (Mcasp)
McASPs are available on your device..........................Topic Page ....................22.1 Introduction ....................22.2 Architecture ......................22.3 Registers SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 870: Introduction
256 bytes = 64 32-bit words in the case of one data pin – Option to bypass Write FIFO and/or Read FIFO independently Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 871: Protocols Supported
(note that the internal bit clock for DIT runs two times faster than the equivalent bit clock for I2S mode, due to the need to generate Biphase Mark Encoded Data). SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 872: Functional Block Diagram
McASP0 has up to 16 serial data pins, n = 15; McASP1 has up to 12 serial data pins, n = 11; One of the DSP's external pins, see your device-specific data manual. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 873: Mcasp To Parallel 2-Channel Dacs
Stereo I2S 2-ch Figure 22-3. McASP to 6-Channel DAC and 2-Channel DAC player Coaxial/ optical On chip S/PDIF encoded Stereo McASP 6-ch 2-ch SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 874: Mcasp To Digital Amplifier
Figure 22-5. McASP as Digital Audio Encoder Stereo I2S On chip LF, RF 2-ch ADC McASP C, LFE S/PDIF 2-ch ADC encoded LS, RS 2-ch ADC Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 875: Industry Standard Compliance Statement
Slot 1 Slot 2 Slot 3 TDM frame FS duration of slot is shown. FS duration of single bit is also supported. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 876: Tdm Format Bit Delays From Frame Sync
Figure 22-8. Inter-IC Sound (I2S) Format AXR[n] Word n−1 Word n Word n+1 right channel left channel right channel 1 to 16 data pins may be supported. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 877: Biphase-Mark Code (Bmc)
0 1 0 0 1 0 1 0 Cell Table 22-1. Biphase-Mark Encoder Previous State at Pin Data (Unencoded) AXR[n] BMC-Encoded Cell Output at AXR[n] SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 878: S/Pdif Subframe Format
DIT mode. If an underrun condition occurs, the DIT resynchronizes to the correct logic level on the AXR[n] pin before continuing with the next transmission. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 879: S/Pdif Frame Format
28 (validity bit) is set to logical 1. Figure 22-11. S/PDIF Frame Format Channel Channel Channel Channel Channel Channel Subframe 1 Subframe 2 Frame 191 Frame 1 Frame 0 SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 880: Definition Of Terms
(2) P - pad bits. Bits b7 to b0, together with the four pad bits, form a slot. (3) In this example, the data is transmitted MSB first, left aligned. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 881: Bit Order And Word Alignment Within A Slot Examples
LSB first, pad with bit 4 8-bit word 12-bit slot Unshaded: bit belongs to word Shaded: bit is a pad bit SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 882: Definition Of Frame And Frame Sync Width
For TDM format, the term time slot is interchangeable with the term slot defined in this section. For DIT format, a Time Slot McASP time slot corresponds to a DIT subframe. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 883: Architecture
In DIT mode, it is possible to use only internally-generated clocks and frame syncs. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 884: Transmit Clock Generator Block Diagram
CLKXP (ACLKXCTL.7) (polarity) CLKXM (internal/external) (ACLKXCTL.5) Divider /1... /32 CLKXDIV AHCLKX (ACLKXCTL[4−0]) HCLKXP (AHCLKXCTL.14) HCLKXM (AHCLKXCTL.15) Divider /1... /4096 AUXCLK HCLKXDIV (AHLKXCTL[11−0]) Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 885: Receive Clock Generator Block Diagram
CLKRDIV (ACLKRCTL[4−0]) HCLKRP HCLKRM (polarity) (internal/external) (AHCLKRCTL.14) (AHCLKRCTL.15) ACLKR RCLK CLKRM ASYNC (internal/external) (ACLKXCTL.6) XCLK (ACLKRCTL.5) CLKRP (from Figure 15) (polarity) (ACLKRCTL.7) SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 886: Frame Sync Generator Block Diagram
(AFSXCTL.0) Internal frame sync AFSX FSXM FSRP (internal/ (AFSRCTL.0) external) (AFSXCTL.1) Internal frame sync AFSR FSRP FSRM (AFSRCTL.0) (internal/external) (AFSRCTL.1) ASYNC (ACLKXCTL.6) Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 887: General Architecture
In DIT mode, in addition to the data, the serializer shifts out other DIT-specific information accordingly (preamble, user data, etc.). The serializer configuration is controlled by SRCTL[n]. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 888: Receive Format Unit
RMASK RPBIT RPAD Programmable rotate by: RROT 0, 4, 8, 12, 16, 20, 24, 28 Bit reverse RRVRS Parallel read from XRBUF[n] Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 889: Transmit Format Unit
RSTAT register. Similarly, the transmit state machine is controlled by the XFMT register, and it reports the McASP status and error conditions in the XSTAT register. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 890 When using these pins in their serial port function, you must clear PFUNC[n] to 0 for each pin, as opposed to PFUNC[n] = 1, which makes the pin a GPIO. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 891: Mcasp I/O Pin Control Block Diagram
Writing 1 clears PDOUT[n] to 0 Writing 0 has no effect PSET[n]: Writing 1 sets PDOUT[n] to 1 Writing 0 has no effect SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 892: Mcasp I/O Pin To Control Register Mapping
PDCLR register only affects pin(s) in concern. To change a pin from 1 to 0: • Set PDCLR[n]. This clears the respective PDOUT[n]. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 893: Operation
Alignment (left or right)? • Order (MSB first, LSB first)? • Pad (if yes, pad with what value)? • Slot size? • Rotate? • Mask? SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 894 GBLCTL should be held at 0. (b) Read back from GBLCTL to ensure the bit(s) to which you wrote are successfully latched in GBLCTL before you proceed. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 895 (b) Read back from GBLCTL to ensure the bit(s) to which you wrote are successfully latched in GBLCTL before you proceed. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 896 (but compatible in terms of slot size) data format. Note that when ASYNC = 0, XCLK is automatically inverted to produce RCLK (note the inversion on the ASYNC multiplexer as shown in Figure 22-16). Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 897: Burst Frame Sync Mode
Slot 1 (0 bit delay) Frame sync: Slot 0 Slot 1 (1 bit delay) Frame sync: Slot 0 Slot 1 (2 bit delay) SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 898 SRCTLn: Program SRMOD to inactive/transmitter/receiver as desired. DISMOD is not applicable and should be left at default. • DITCSRA[n], DITCSRB[n], DITUDRA[n], DITUDRB[n]: Not applicable. Leave at default. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 899 For each slot, the TDM sequencer checks the respective bit in either XTDM or RTDM to determine if the McASP should transmit/receive in that time slot. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 900: Transmit Dma Event (Axevt) Generation In Tdm Time Slots
For this special DIR mode, the control registers can be configured just as for TDM mode, except set RMOD in AFSRCTL to 384 to receive 384 time slots. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 901 XMASK = 00FF FFFFh to 0000 FFFFh (depending upon whether 24, 23, 22, 21, 20, 19, 18, 17, or 16 valid audio data bits are present) • XPAD = 00 (pad extra bits with 0) SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 902 SRCTLn: Set SRMOD = 1 (transmitter) for the DIT pins. DISMOD field is don't care for DIT mode. • DITCSRA[n], DITCSRB[n]: Program the channel status bits as desired. • DITUDRA[n], DITUDRB[n]: Program the user data bits as desired. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 903 Either the CPU or the DMA can be used to service the McASP through any of these two peripheral ports. The CPU and DMA usages are discussed in Section 22.2.4.3.4 Section 22.2.4.3.5. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 904: Channel Status And User Data For Each Dit Block
Defined by DITCSRA5, DITCSRB5, DITDRA5, DITUDRB5 1 (L) DITCSRA5[0] DITUDRA5[0] 2 (R) DITCSRB5[0] DITUDRB5[0] … … … … … 1 (L) DITCSRA5[31] DITUDRA5[31] 2 (R) DITCSRB5[31] DITUDRB5[31] Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 905: Dsp Service Time Upon Transmit Dma Event (Axevt)
4 ACLKX cycles This is not the same as AUXCLK. The DSP uses SYSCLK2 as the McASP system clock source. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 906: Dsp Service Time Upon Receive Dma Event (Arevt)
+ 4 ACLKR system clocks cycles This is not the same as AUXCLK. The DSP uses SYSCLK2 as the McASP system clock source. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 907 XBUFn. For example, the XRBUF associated with transmit serializer 2 is named XBUF2. Similarly, XRBUF for the serializers configured as receivers is given the name RBUFn. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 908: Dma Events In An Audio Example-Two Events
Note the difference between DMA event generation and the CPU interrupt generation. DMA events are generated automatically upon data ready; whereas CPU interrupt generation needs to be enabled in the XINTCTL/RINTCTL register. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 909: Mcasp Audio Fifo (Afifo) Block Diagram
Note that when the WFIFO is first enabled, it will immediately issue a transmit DMA request to the host. This is because it begins in an empty state, and is therefore ready to accept data. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 910 If only the RFIFO is enabled and a transmit DMA request and receive DMA request occur simultaneously, priority is given to the receive DMA request. Once a transfer is in progress, it is allowed to complete. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 911: Transmit Bitstream Data Alignment
WORD = Word size rounded up to the nearest multiple of 4; SLOT = slot size; % = modulo operator To transmit in I2S format, use MSB first, left aligned, and also select XDATDLY = 01 (1 bit delay) SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 912: Data Flow Through Transmit Format Unit
P ... P, L, ... M−1, M P ... P, L, ... M−1, M (l) Out: LSB first, RIGHT aligned (p) Out: LSB first, RIGHT aligned Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 913: Receive Bitstream Data Alignment
WORD = Word size rounded up to the nearest multiple of 4; SLOT = slot size; % = modulo operator To transmit in I2S format, select MSB first, left aligned, and also select RDATDLY = 01 (1 bit delay) SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 914: Data Flow Through Receive Format Unit
P ... P, L, ... M−1, M P ... P, L, ... M−1, M (h) In: LSB first, RIGHT aligned (d) In: LSB first, RIGHT aligned Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 915 In addition to the external AMUTEIN input, the AMUTE device pin output may be asserted when one of the error interrupt flags is set and its mute function is enabled in AMUTE. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 916: Audio Mute (Amute) Block Diagram
Error is detected (and enabled) Drives AMUTE pin AMUTE pin is MUXED with GPIO, so GPIO function must be set to McASP for automatic mute function Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 917 Current frame is not resynchronized. The number of bits in the current frame is completed. The next frame sync, which occurs after the current frame is completed, will be resynchronized. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 918 While XDMAERR occurs infrequently, an occurrence indicates a serious loss of synchronization between the McASP and the DMA or CPU. You should reinitialize both the McASP transmitter and the DMA to resynchronize them. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 919 (i) receive clock failure interrupt enable bit (RCKFAIL) in the receiver interrupt control register (RINTCTL) (ii) mute option (RCKFAIL) in the mute control register (AMUTE) SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 920: Transmit Clock Failure Detection Circuit Block Diagram
XCKFAIL XCLKCHK[23−16] True Counter>XMAX? XMAX This is not the same as AUXCLK. The DSP uses SYSCLK2 as the McASP system clock. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 921: Receive Clock Failure Detection Circuit Block Diagram
RCKFAIL RCLKCHK[23−16] True Counter>RMAX? RMAX This is not the same as AUXCLK. The DSP uses SYSCLK2 as the McASP system clock source. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 922: Serializers In Loopback Mode
(a) DLBEN = 1 (loopback enabled) DLBEN = 1 (loopback enabled) ORD = 0 (even receive, ORD = 1 (odd receive, odd transmit) even transmit) Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 923: Reset Considerations
The PSC acts as a master controller for power management for all of the peripherals on the device. For information on power management procedures using the PSC, see the Power and Sleep Controller (PSC) chapter. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 924: Registers
Current transmit TDM time slot register Section 22.3.34 XCLKCHK Transmit clock check control register Section 22.3.35 XEVTCTL Transmitter DMA event control register Section 22.3.36 924 Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 925 Serializer control register 13 Section 22.3.37 1B8h SRCTL14 Serializer control register 14 Section 22.3.37 1BCh SRCTL15 Serializer control register 15 Section 22.3.37 SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 926 Reads from XRBUF[n] by way of RBUFn by the CPU/EDMA can only occur through the peripheral configuration port when RBUSEL = 1 in RFMT. 926 Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 927: Register Bit Restrictions
AFSRCTL FSRP AFSRCTL FSRM AFSRCTL FRWID AFSRCTL RMOD ACLKXCTL CLKXDIV ACLKXCTL CLKXM ACLKXCTL ASYNC ACLKXCTL CLKXP ACLKRCTL CLKRDIV ACLKRCTL CLKRM ACLKRCTL CLKRP SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 928: Revision Identification Register (Rev)
LEGEND: R = Read only; -n = value after reset Table 22-11. Revision Identification Register (REV) Field Descriptions Field Value Description 31-0 4430 0A02h Identifies revision of peripheral. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 929: Pin Function Register (Pfunc)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset A If writing to this field, always write the default value for future device compatibility. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 930: Pin Function Register (Pfunc) Field Descriptions
If writing to this field, always write the default value for future device compatibility. 15-0 AXR[15-0] Determines if AXR[n] pin functions as McASP or GPIO. Pin functions as McASP pin. Pin functions as GPIO pin. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 931: Pin Direction Register (Pdir)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset A If writing to this field, always write the default value for future device compatibility. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 932: Pin Direction Register (Pdir) Field Descriptions
If writing to this field, always write the default value for future device compatibility. 15-0 AXR[15-0] Determines if AXR[n] pin functions as an input or output. Pin functions as input. Pin functions as output. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 933: Pin Data Output Register (Pdout)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset A If writing to this field, always write the default value for future device compatibility. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 934: Pin Data Output Register (Pdout) Field Descriptions
Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1. Pin drives low. Pin drives high. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 935: Pin Data Input Register (Pdin)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset A If writing to this field, always write the default value for future device compatibility. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 936: Pin Data Input Register (Pdin) Field Descriptions
If writing to this field, always write the default value for future device compatibility. 15-0 AXR[15-0] Logic level on AXR[n] pin. Pin is logic low. Pin is logic high. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 937: Pin Data Set Register (Pdset)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset A If writing to this field, always write the default value for future device compatibility. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 938: Pin Data Set Register (Pdset) Field Descriptions
Allows the corresponding AXR[n] bit in PDOUT to be set to a logic high without affecting other I/O pins controlled by the same port. No effect. PDOUT[n] bit is set to 1. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 939: Pin Data Clear Register (Pdclr)
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset A If writing to this field, always write the default value for future device compatibility. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 940: Pin Data Clear Register (Pdclr) Field Descriptions
Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port. No effect. PDOUT[n] bit is cleared to 0. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 941: Global Control Register (Gblctl)
XHCLKRST Transmit high-frequency clock divider reset enable bit. Transmit high-frequency clock divider is held in reset. Transmit high-frequency clock divider is running. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 942 Receive clock divider is held in reset. When the clock divider is in reset, it passes through a divide-by-1 of its input. Receive clock divider is running. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 943: Audio Mute Control Register (Amute)
Drive is disabled. Detection of transmit underrun error is ignored by AMUTE. Drive is enabled (active). Upon detection of transmit underrun error, AMUTE is active and is driven according to MUTEN bit. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 944 AMUTE pin is disabled, pin goes to tri-state condition. AMUTE pin is driven high if error is detected. AMUTE pin is driven low if error is detected. Reserved Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 945: Digital Loopback Control Register (Dlbctl)
Even serializers N transmit to odd serializers N+1 that receive. The corresponding serializers must be programmed properly. DLBEN Loopback mode enable bit. Loopback mode is disabled. Loopback mode is enabled. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 946: Digital Mode Control Register (Ditctl)
GBLCTL to change DITEN. DIT mode is disabled. Transmitter operates in TDM or burst mode. DIT mode is enabled. Transmitter operates in DIT encoded mode. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 947: Receiver Global Control Register (Rgblctl)
Receive clock divider reset enable bit. A write to this bit affects the RCLKRST bit of GBLCTL. Receive clock divider is held in reset. Receive clock divider is running. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 948: Receive Format Unit Bit Mask Register (Rmask)
(RPAD and RPBIT bits in RFMT). Corresponding bit of receive data (after passing through reverse and rotate units) is returned to CPU or DMA. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 949: Receive Bit Stream Format Register (Rfmt)
This field only applies when RPAD = 2h. Pad with bit 0 value. 1h-1Fh Pad with bit 1 to bit 31 value. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 950 Rotate right by 16 bit positions. Rotate right by 20 bit positions. Rotate right by 24 bit positions. Rotate right by 28 bit positions. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 951: Receive Frame Sync Control Register (Afsrctl)
A rising edge on receive frame sync (AFSR) indicates the beginning of a frame. A falling edge on receive frame sync (AFSR) indicates the beginning of a frame. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 952: Receive Clock Control Register (Aclkrctl)
ACLKXCTL.ASYNC = 0 (see Section 22.3.29 for a description for the ASYNC bit). Divide-by-1 Divide-by-2 2h-1Fh Divide-by-3 to divide-by-32 Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 953: Receive High-Frequency Clock Control Register (Ahclkrctl)
HCLKRDIV 0-FFFh Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR. Divide-by-1 Divide-by-2 2h-FFFh Divide-by-3 to divide-by-4096 SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 954: Receive Tdm Time Slot Register (Rtdm)
Receive TDM time slot n is inactive. The receive serializer does not shift in data during this slot. Receive TDM time slot n is active. The receive serializer shifts in data during this slot. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 955: Receiver Interrupt Control Register (Rintctl)
Interrupt is disabled. A receiver overrun interrupt does not generate a McASP receive interrupt (RINT). Interrupt is enabled. A receiver overrun interrupt generates a McASP receive interrupt (RINT). SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 956: Receiver Status Register (Rstat)
RINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 to this bit has no effect. Receive clock failure did not occur. Receive clock failure did occur. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 957: Current Receive Tdm Time Slot Registers (Rslot)
However, TDM time slot counter may count to 383 when used to receive a DIR block (transferred over TDM format). SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 958: Receive Clock Check Control Register (Rclkchk)
McASP system clock divided by 32 McASP system clock divided by 64 McASP system clock divided by 128 McASP system clock divided by 256 9h-Fh Reserved Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 959: Receiver Dma Event Control Register (Revtctl)
Receive data DMA request enable bit. If writing to this field, always write the default value of 0. Receive data DMA request is enabled. Reserved. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 960: Transmitter Global Control Register (Xgblctl)
Receive clock divider reset enable bit. A read of this bit returns the RCLKRST bit value of GBLCTL. Writes have no effect. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 961: Transmit Format Unit Bit Mask Register (Xmask)
McASP in place of the original bit. Corresponding bit of transmit data (before passing through reverse and rotate units) is transmitted out the McASP. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 962: Transmit Bit Stream Format Register (Xfmt)
This field only applies when XPAD = 2h. Pad with bit 0 value. 1-1Fh Pad with bit 1 to bit 31 value. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 963 Rotate right by 16 bit positions. Rotate right by 20 bit positions. Rotate right by 24 bit positions. Rotate right by 28 bit positions. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 964: Transmit Frame Sync Control Register (Afsxctl)
A rising edge on transmit frame sync (AFSX) indicates the beginning of a frame. A falling edge on transmit frame sync (AFSX) indicates the beginning of a frame. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 965: Transmit Clock Control Register (Aclkxctl)
CLKXDIV 0-1Fh Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX. Divide-by-1 Divide-by-2 2h-1Fh Divide-by-3 to divide-by-32 SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 966: Transmit High-Frequency Clock Control Register (Ahclkxctl)
HCLKXDIV 0-FFFh Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX. Divide-by-1 Divide-by-2 2h-FFFh Divide-by-3 to divide-by-4096 Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 967: Transmit Tdm Time Slot Register (Xtdm)
Transmit TDM time slot n is active. The transmit serializer shifts out data during this slot according to the serializer control register (SRCTL). SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 968: Transmitter Interrupt Control Register (Xintctl)
Interrupt is disabled. A transmitter underrun interrupt does not generate a McASP transmit interrupt (XINT). Interrupt is enabled. A transmitter underrun interrupt generates a McASP transmit interrupt (XINT). Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 969: Transmitter Status Register (Xstat)
XINTCTL is set. This bit is cleared by writing a 1 to this bit. Writing a 0 has no effect. Transmit clock failure did not occur. Transmit clock failure did occur. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 970: Current Transmit Tdm Time Slot Register (Xslot)
B preamble. TDM function is not supported for > 32 time slots. However, TDM time slot counter may count to 383 when used to transmit a DIT block. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 971: Transmit Clock Check Control Register (Xclkchk)
McASP system clock divided by 32 McASP system clock divided by 64 McASP system clock divided by 128 McASP system clock divided by 256 9h-Fh Reserved SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 972: Transmitter Dma Event Control Register (Xevtctl)
Transmit data DMA request enable bit. If writing to this field, always write the default value of 0. Transmit data DMA request is enabled. Reserved. Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 973: Serializer Control Registers (Srctln)
Drive on pin is logic low. Drive on pin is logic high. SRMOD 0-3h Serializer mode bit. Serializer is inactive. Serializer is transmitter. Serializer is receiver. Reserved SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 974: Dit Left Channel Status Registers (Ditcsra0-Ditcsra5)
Figure 22-72. DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) DITCSRBn R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 975: Dit Left Channel User Data Registers (Ditudra0-Ditudra5)
Figure 22-74. DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) DITUDRBn R/W-0 LEGEND: R/W = Read/Write; -n = value after reset SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 976: Transmit Buffer Registers (Xbufn)
Accessing RBUF registers not implemented on a specific DSP may cause improper device operation. Figure 22-76. Receive Buffer Registers (RBUFn) RBUFn R/W-0 LEGEND: R/W = Read/Write; -n = value after reset Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 977: Afifo Revision Identification Register (Afiforev)
LEGEND: R = Read only; -n = value after reset Table 22-47. AFIFO Revision Identification Register (AFIFOREV) Field Descriptions Field Value Description 31-0 4431 1100h Identifies revision of Audio FIFO. SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 978: Write Fifo Control Register (Wfifoctl)
McASP serializers (not the number of channels) used as transmitters. This value must be set prior to enabling the Write FIFO. 0 words 1 word 2 words 3h-10h 3-16 words 11h-FFh Reserved Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 979: Write Fifo Status Register (Wfifosts)
1 word currently in Write FIFO. 2 words currently in Write FIFO. 3h-40h 3 to 64 words currently in Write FIFO. 41h-FFh Reserved SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 980: Read Fifo Control Register (Rfifoctl)
McASP serializers used as receivers. This value must be set prior to enabling the Read FIFO. 0 words 1 word 2 words 3h-10h 3-16 words 11h-FFh Reserved Multichannel Audio Serial Port (McASP) SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 981: Read Fifo Status Register (Rfifosts)
1 word currently in Read FIFO. 2 words currently in Read FIFO. 3h-40h 3 to 64 words currently in Read FIFO. 41h-FFh Reserved SPRUH90B – March 2013 Multichannel Audio Serial Port (McASP) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 982: Multimedia Card (Mmc)/Secure Digital (Sd) Card Controller
........................... Topic Page ....................23.1 Introduction ....................23.2 Architecture ..............23.3 Procedures for Common Operations 1000 ...................... 23.4 Registers 1012 Multimedia Card (MMC)/Secure Digital (SD) Card Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 983: Introduction
MMC/SD single-block write using CPU • MMC/SD single-block write using EDMA • MMC/SD multiple-block read using CPU • MMC/SD multiple-block read using EDMA SPRUH90B – March 2013 Multimedia Card (MMC)/Secure Digital (SD) Card Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 984: Industry Standard(S) Compliance Statement
Figure 23-2. MMC/SD Controller Interface Diagram MMCs or SD cards MMC/SD Native controller signals Native packets DAT0, DAT0-3, or DAT0-7 Memory EDMA Multimedia Card (MMC)/Secure Digital (SD) Card Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 985: Clock Control
The function clock determines the operational frequency of the MMC/SD controller and is the input clock to the MMC/SD card(s). SPRUH90B – March 2013 Multimedia Card (MMC)/Secure Digital (SD) Card Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 986: Signal Descriptions
For more detailed information, refer to the supported MMC and SD specifications in Section 23.1.5. Multimedia Card (MMC)/Secure Digital (SD) Card Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 987: Mmc/Sd Mode Write Sequence Timing Diagram
BUSY bit: The CRC status information is followed by a continuous stream of low busy bits until all of the data has been programmed into the flash memory on the card. SPRUH90B – March 2013 Multimedia Card (MMC)/Secure Digital (SD) Card Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 988: Data Flow In The Input/Output Fifo
EDMA events and interrupts based on the amount of data in the FIFO and a programmable number of bytes received/transmitted. Flags are set when the FIFO is full or empty. Multimedia Card (MMC)/Secure Digital (SD) Card Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 989: Fifo Operation Diagram
16-bit DRR 512-bits of data received by FIFO Step 6: EDMA read reception data 16-bit DXR 16-bit DRR shifter shifter SPRUH90B – March 2013 Multimedia Card (MMC)/Secure Digital (SD) Card Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 990: Data Flow In The Data Registers (Mmcdrr And Mmcdxr)
MMCDRR or MMCDXR registers Support byten = ”1111” Support byten = ”0111” Support byten = ”0011” Support byten = ”0001” Multimedia Card (MMC)/Secure Digital (SD) Card Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 991: Fifo Operation During Card Read Operation
MMC block length register (MMCBLEN) and the MMC numbers of blocks register (MMCNBLK) settings. SPRUH90B – March 2013 Multimedia Card (MMC)/Secure Digital (SD) Card Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 992: Fifo Operation During Card Read Diagram
FIFO check 2 FIFO full Capture data, Increment counter Idle, DMA pending Counter =FIFOLEV done Generate DMA done Reset counter Multimedia Card (MMC)/Secure Digital (SD) Card Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 993: Fifo Operation During Card Write Operation
23.2.8.2 Hardware Reset Considerations A hardware reset of the processor causes the MMC/SD controller registers to return to their default values after reset. SPRUH90B – March 2013 Multimedia Card (MMC)/Secure Digital (SD) Card Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 994: Fifo Operation During Card Write Diagram
FIFO check 2 FIFO empty Send data, DMA pending Increment counter Idle, DMA pending Counter =FIFOLEV done Generate DMA done Reset counter Multimedia Card (MMC)/Secure Digital (SD) Card Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 995: Initialization
To enable the associated interrupt request, set the corresponding bit in MMCIM. To disable the associated interrupt request, clear the corresponding bit. Load zeros into the bits that are not used in the MMC/SD mode. SPRUH90B – March 2013 Multimedia Card (MMC)/Secure Digital (SD) Card Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 996 CRC errors of command response, data read, and data write. If the interrupt request is enabled (ECRCRS/ECRCRD/ECRCWR = 1 in MMCIM), the CPU is notified of the CRC error by an interrupt. Multimedia Card (MMC)/Secure Digital (SD) Card Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 997 The DRFUL bit is not typically used to control data transfers; rather, it is checked during recovery from an error condition. There is no interrupt associated with the DRFUL bit. SPRUH90B – March 2013 Multimedia Card (MMC)/Secure Digital (SD) Card Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 998: Interrupt Support
For read operations: The MMC controller has received data without a CRC error. For write operations: The MMC controller has finished sending data. 998 Multimedia Card (MMC)/Secure Digital (SD) Card Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 999: Dma Event Support
Sleep Controller (PSC) chapter. 23.2.13 Emulation Considerations The MMC/SD peripheral is not affected by emulation halt events (such as breakpoints). SPRUH90B – March 2013 Multimedia Card (MMC)/Secure Digital (SD) Card Controller Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...
Page 1000: Procedures For Common Operations
MMC card identification procedure terminates. The sequence of events in this operation is shown in Figure 23-11. 1000 Multimedia Card (MMC)/Secure Digital (SD) Card Controller SPRUH90B – March 2013 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated...