Radyne DMD2401 LB Installation And Operation Manual page 117

User Interfaces
<1> Alarm 2 Mask
<1> Alarm 3 Mask
<1> Alarm 4 Mask
<1> Common Alarm 1
Mask
<1> Reserved
<1> BER Measure
Period
<24> Rx Circuit ID
<1> Rx Terrestrial
Loopback
<1> Rx Baseband
Loopback
<1> Rx IF Loopback
<1> Reserved
<1> Data Invert
4-80
DMD2401 LB/ST L-Band Satellite Modem and ODU Driver
Bit 0 = Buffer Underflow
Bit 1 = Buffer Overflow
Bit 2 = Buffer Under 10%
Bit 3 = Buffer Over 90%
Bit 4 = Receive FPGA Configuration Fault
Bit 5 = Rx LNB Fault, LBST Only
Bit 6 - 7 = Spares
(0 = Mask, 1 = Allow)
Bit 0 = IF Synthesizer Lock Detect Fault
Bit 1 = Rx Oversample PLL Lock Detect Fault
Bit 2 = Buffer Clock PLL Lock Detect Fault
Bit 3 = Viterbi Decoder Lock Fault
Bit 4 = Sequential Decoder Lock Fault
Bit 5 = Rx 2047 Test Pattern Lock Fault
Bit 6 = External Reference PLL Lock Fault
Bit 7 = Frame Sync Fault
(0 = Mask, 1 = Allow)
Bit 0 = Buffer Clock Activity Detect Fault
Bit 1 = External BNC Activity Detect Fault
Bit 2 = Rx Satellite Clock Activity Detect Fault
Bit 3 = External Reference PLL Activity Fault
Bits 4 - 7 = Spares
(0 = Mask, 1 = Allow)
Bit 0 = -12 V Alarm
Bit 1 = +12 V Alarm
Bit 2 = +5 V alarm
Bit 3 = Temperature
Bit 4 = Interface FPGA Fault
Bit 5 = Battery Fault
Bit 6 = RAM/ROM Fault
Bit 7 = Spare
(0 = Mask, 1 = Allow)
Set to Zero
Unsigned Binary Number of Bits in Measurement Period in
Powers of Ten (ex: 6 = 10
24 ASCII Characters
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
Set to Zero
0 = Normal, 1 = Invert
Note: The following byte applies only if an
6
Bits)
TM075 – Rev. 1.3