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DMD2401/DMD2401L/DMD2401 IBS/IDR Satellite Modem
<1>
Alarm 1 Mask
Major Alarms
<1>
Alarm 2 Mask
Minor Alarms
<1>
Common Alarm 1
Mask
<24>
Tx Circuit ID
<1>
Tx Terrestrial
Loopback
<1>
Tx Baseband
Loopback
<1>
Reserved
<1>
Reserved
<1>
Data Invert
<1>
Framing
TM065 - Rev. 3.3
Bit 0 = Transmit Processor Fault
Bit 1 = Transmit Output Power Level Fault
Bit 2 = Transmit Oversample PLL Lock Fault
Bit 3 = Transmit Composite Clock PLL Lock Fault
Bit 4 = IF Synthesizer Lock Fault
Bit 5 = Transmit FPGA Configuration Fault
Bit 6 = Transmit Forced Alarm
Bit 7 = External Reference PLL Lock Fault
(0 = Mask, 1 = Allow)
Bit 0 = Terrestrial Clock Activity Detect Fault
Bit 1 = Internal Clock Activity Detect Fault
Bit 2 = Tx Sat Clock Activity Detect Fault
Bit 3 = Tx Data Activity Detect Fault
Bit 4 = Tx Data AIS Detect Fault
Bit 5 = Transmit EXT BNC Clock Activity Detect Fault
Bit 6 = Transmit Reed-Solomon Fault
Bit 7 = Tx BUC Fault, LBST only
(0 = Mask, 1 = Allow)
Bit 0 = -12 V Alarm
Bit 1 = +12 V Alarm
Bit 2 = +5 V Alarm
Bit 3 = Interface FPGA
Bit 4 = Temperature
Bit 5 = Battery Fault
Bit 6 = RAM/ROM Fault
Bit 7 = Spare
(0 = Mask, 1 = Allow)
24 ASCII Characters
0 = Disabled, 1 = Enabled
0 = Disabled, 1 = Enabled
Ignore
Ignore
0 = Normal, 1 = Invert
Note: The following byte applies only if an
Asynchronous, IDR or IBS Interface is installed. If not,
ignore.
0 = No Framing
1 = 1/16 IBS
2 = 1/16 Async
3 = 96 Kbit IDR
Note: The following three bytes applies only if an
Asynchronous, Interface Card is installed. If not, ignore.
User Interfaces
4-49
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